Analog-to-digital converter controllers including configurable contexts

• US 10,536,156 B1
• Filed: 10/16/2018
• Issued: 01/14/2020
• Est. Priority Date: 10/16/2018
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Senapati, Ashish, Kilzer, Kevin, Pulipaka, Prashanth
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US16/162,135
• Time in Patent Office: 455 Days
• Field of Search: 341 51- 75, 341130-160
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/1205 Multiplexed conversion systems
• CPC Class Codes: H03M 1/1225 using time-division multiplexing

Abstract

Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.

Claims

1. An analog-to-digital converter (ADC) controller, the ADC controller comprising:

a number of input channels;

an ADC selectively coupled to each input channel of the number of input channels;

a number of contexts operatively coupled to the ADC, each context associated with an input channel of the number of input channels, each context having at least one register for storing at least one configurable parameter; and

a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.

2. The ADC controller of claim 1, wherein one configurable parameter of the at least one configurable parameter of each context indicates whether the context is to be included in the programmed conversion sequence.

3. The ADC controller of claim 2, wherein the one configurable parameter that indicates whether or not the context is to be included in the programmed conversion sequence comprises a sequence enable bit.

4. The ADC controller of claim 1, wherein one configurable parameter of the at least one configurable parameter of each context comprises an interrupt parameter.

5. The ADC controller of claim 1, further comprising a context selector operatively coupled to the sequencer and configured to select a context of the number of contexts based on the programmed conversion sequence.

6. The ADC controller of claim 1, further comprising a peripheral bus operatively coupled to each of the number of contexts and the sequencer.

7. The ADC controller of claim 6, wherein each context is configured to receive a signal via the peripheral bus for configuring the at least one configurable parameter.

8. The ADC controller of claim 1, further comprising an input channel selector operatively coupled between the number of contexts and the number of input channels, the input channel selector configured to select an input channel of the number of input channels based on a signal from at least one of the number of contexts.

9. A method of performing an analog-to-digital (A/D) conversion sequence, the method comprising:

converting an input signal of a first input channel associated with a first context of a number of contexts to a first digital signal;

determining if a continuous operation bit of the first context is asserted;

determining if a sequence enable bit of the first context is asserted;

in response to determining that the continuous operation bit of the first context is not asserted and the sequence enable bit of the first context is asserted, selecting a second context of the number of contexts; and

converting an input signal of a second input channel associated with the second context to a second digital signal.

10. The method of claim 9, further comprising:

determining if a continuous operation bit of the second context is asserted;

determining if a sequence enable bit of the second context is asserted;

in response to determining that the continuous operation bit of the second context is not asserted and the sequence enable bit of the second context is asserted, selecting a third context of the number of contexts; and

converting an input signal of a third input channel associated with the third context to a third digital signal.

11. The method of claim 9, further comprising:

determining if an interrupt flag for the first context has been triggered;

in response to determining that the interrupt flag for the first context has been triggered, determining if a stop on interrupt bit of the first context is asserted; and

in response to determining that the stop on interrupt bit of the first context is not asserted, converting the input signal of the first input channel associated with the first context to the first digital signal.

12. The method of claim 9, further comprising in response to determining that either the continuous operation bit of the first context is asserted or the sequence enable bit of the first context is not asserted, clearing an A/D conversion status bit of the first context.

13. The method of claim 9, further comprising detecting a trigger prior to converting the input signal of the first input channel.

14. The method of claim 9, further comprising asserting an analog-to-digital (A/D) conversion status bit prior to converting the input signal of the first input channel.