Data processing method and apparatus

• US 10,536,163 B2
• Filed: 07/04/2017
• Issued: 01/14/2020
• Est. Priority Date: 07/04/2016
• Status: Active Grant

• Current Assignee: Sisp Technologies Ltd.
• Original Assignee: Sisp Technologies Ltd.
• Inventors: Marlow, Stuart, Stavrinou, Nicholas
• Primary Examiner(s): Williams, Howard
• Application Number:
  US16/314,868
• Publication Number:
  US 20190312586A1
• Time in Patent Office: 924 Days
• Field of Search: None
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: H03M 7/3064 Segmenting
• CPC Class Codes: H03M 7/3095 using variable length segments

Abstract

A method of compression is disclosed in which an input sequence of bits is divided into a plurality of portions. Each portion is sub-divided into a plurality of sub-divisions. Frequency analysis is performed to determine the number of occurrences of each sub-division permutation and a processed sequence of bits is generated based on the frequency analysis. The processed sequence of bits includes extraction information for use in reconstructing said input sequence of bits from said processed sequence of bits. The extraction information comprises sub-division order information identifying an ordered sequence comprising each possible sub-division permutation arranged in order of how many times, within said input sequence of bits, a portion comprises a sub-division having bits arranged in that possible sub-division permutation. The sub-division order information includes an index value representing the order of the corresponding ordered sequence, based on a preconfigured mapping between said index value and the order of the corresponding ordered sequence.

Claims

1. A method of processing data comprising an input sequence of bits, the method comprising the steps of:

dividing the input sequence of bits into a plurality of portions;

respectively sub-dividing each portion into a plurality of sub-divisions comprising at least a first sub-division and a second sub-division, wherein each sub-division of the plurality of sub-divisions comprises at least one bit, wherein the at least one bit of each first sub-division is arranged in a respective first sub-division permutation, and wherein the at least one bit of each second sub-division is arranged in a respective second sub-division permutation;

performing frequency analysis;

to determine, for each of a plurality of possible first sub-division permutations, how many times, within said input sequence of bits, a portion comprises a first sub-division having bits arranged in that possible first sub-division permutation; and

to determine, for each of a plurality of possible second sub-division permutations, how many times, within said input sequence of bits, a portion comprises a second sub-division having bits arranged in that possible second sub-division permutation; and

forming a processed sequence of bits based on said frequency analysis;

wherein said forming a processed sequence of bits further comprises including extraction information in the processed sequence of bits, said extraction information for use in reconstructing said input sequence of bits from said processed sequence of bits; and

wherein the extraction information comprises at least one of;

first sub-division order information identifying an ordered sequence comprising each possible first sub-division permutation arranged in order of how many times, within said input sequence of bits, a portion comprises a first sub-division having bits arranged in that possible first sub-division permutation; and

second sub-division order information identifying an ordered sequence comprising each possible second sub-division permutation arranged in order of how many times, within said input sequence of bits, a portion comprises a second sub-division having bits arranged in that possible second sub-division permutation; and

wherein the at least one of said first sub-division order information and said second sub-division order information comprises an index value, representing the order of the corresponding ordered sequence, based on a preconfigured mapping between said index value and the order of the corresponding ordered sequence.

2. A method according to claim 1, wherein said extraction information is configured for use in identifying how the said plurality of possible first (or second) sub-division permutations are grouped into sets.

3. A method according to claim 2, wherein said extraction information identifies how many first (or second) sub-division permutations each set comprises.

4. A method according to claim 3, wherein the extraction information is further configured to identify how each portion is sub-divided into a plurality of sub-divisions.

5. A method according to claim 4, wherein the extraction information is further configured to identify how many bits each first sub-division comprises and how many bits each second sub-division comprises.

6. A method according to 3, wherein the extraction information is further configured to identify how many bits the input sequence of bits comprises.

7. A method according to claim 2, wherein the extraction information is further configured to identify how each portion is sub-divided into a plurality of sub-divisions.

8. A method according to claim 7, wherein the extraction information is further configured to identify how many bits each first sub-division comprises and how many bits each second sub-division comprises.

9. A method according to claim 2, wherein the extraction information is further configured to identify how many bits the input sequence of bits comprises.

10. A method according to claim 1, wherein the extraction information is further configured to identify how each portion is sub-divided into a plurality of sub-divisions.

11. A method according to claim 10, wherein the extraction information is further configured to identify how many bits each first sub-division comprises and how many bits each second sub-division comprises.

12. A method according to claim 11, wherein the extraction information is further configured to identify how many bits the input sequence of bits comprises.

13. A method according to claim 10, wherein the extraction information is further configured to identify how many bits the input sequence of bits comprises.

14. A method according to claim 1, wherein the extraction information is further configured to identify how many bits the input sequence of bits comprises.