Dynamic current sink for stabilizing low dropout linear regulator

• US 10,539,972 B2
• Filed: 12/26/2017
• Issued: 01/21/2020
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Chin-Hsun, Lin, Hao-Yuan, Chou, Chia-Hua
• Primary Examiner(s): Tran, Nguyen
• Assistant Examiner(s): Singh, David A.
• Application Number:
  US15/853,970
• Publication Number:
  US 20180120874A1
• Time in Patent Office: 756 Days
• Field of Search: None
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G05F 1/462 as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
• CPC Class Codes: G05F 1/467 Sources with noise compensation
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/563 including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/569 for protection
• CPC Class Codes: G05F 1/571 with overvoltage detector
• CPC Class Codes: G05F 1/573 with overcurrent detector
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Claims

1. A dynamic current sink for stabilizing an output voltage at an output node of an LDO (Low Dropout Linear Regulator), comprising:

a comparator, for comparing a first reference signal with a signal obtained from the LDO to generate a comparison result, wherein the comparison result indicates whether an overshoot output voltage related to the LDO occurs;

a control circuit, coupled to the comparator, for receiving the comparison result to generate a first control signal, and generating a second control signal according to the comparison result;

a first switching circuit, coupled to the output node of the LDO, a reference voltage and the first control signal, for selectively connecting or disconnecting the output node of the LDO to the reference voltage according to the first control signal;

a second switching circuit, coupled to the output node of the LDO, the reference voltage and the second control signal, for selectively connecting or disconnecting the output node of the LDO to the reference voltage according to the second control signal.

2. The dynamic current sink of claim 1, wherein when the comparison result indicates that the overshoot output voltage related to the LDO occurs, the control circuit generates the first control signal to control the first switching circuit to connect the output node of the LDO to the reference voltage to provide a discharge current;

and when the comparison result indicates that there is no overshoot output voltage related to the LDO, the control circuit generates the first control signal to control the first switching circuit to disconnect the output node of the LDO to the reference voltage.

3. The dynamic current sink of claim 1, wherein the signal is obtained by comparing a feedback voltage of the LDO with a second reference signal.

4. The dynamic current sink of claim 1, wherein the signal is obtained from a loading current of the LDO.

5. The dynamic current sink of claim 4, wherein the signal is extracted from the loading current of the LDO, and the signal and the loading current of the LDO has a predetermined ratio.

6. The dynamic current sink of claim 1, wherein the first switching circuit and the second switching circuit are used to provide a first discharge current and a second discharge current to the output node of the LDO, respectively, and the first discharge current and the second discharge current have different slopes over time axis.

7. The dynamic current sink of claim 1, wherein the control circuit comprises:

a transistor, for receiving the comparison result to generate an intermediate signal; and

a logic circuit module, coupled between the transistor and the first switching circuit, for generating the first control signal according to the intermediate signal.

8. The dynamic current sink of claim 7, wherein the control circuit further comprises a capacitor coupled between the logic circuit module and the first switching circuit.

9. An LDO (Low Dropout Linear Regulator), comprising:

a first comparator, for comparing a feedback voltage with a first reference signal to generate a first control signal;

a first switching circuit, coupled to a supply voltage, an output node of the LDO and the first control signal, for selectively connecting or disconnecting the supply voltage to the output node of the LDO;

a dynamic current sink, coupled to the output node of the LDO, for determining whether an overshoot output voltage relates to the LDO occurs to selectively provide a discharge current to the output node of the LDO or not provide the discharge current to the output node of the LDO;

wherein the dynamic current sink comprises;

a second comparator, for comparing a second reference signal with a signal obtained from the LDO to generate a comparison result, wherein the comparison result indicates whether the overshoot output voltage relates to the LDO occurs;

a control circuit, coupled to the second comparator, for generating a second control signal and a third control signal according to the comparison result;

a second switching circuit, coupled to the output node of the LDO, a reference voltage and the second control signal, for selectively connecting or disconnecting the output node of the LDO to the reference voltage according to the second control signal; and

a third switching circuit, coupled to the output node of the LDO, the reference voltage and the third control signal, for selectively connecting or disconnecting the output node of the LDO to the reference voltage according to the third control signal.

10. The LDO of claim 9, wherein when the comparison result indicates that the overshoot output voltage related to the LDO occurs, the control circuit generates the second control signal to control the second switching circuit to connect the output node of the LDO to the reference voltage to provide a discharge current;

and when the comparison result indicates that there is no overshoot output voltage related to the LDO, the control circuit generates the second control signal to control the second switching circuit to disconnect the output node of the LDO to the reference voltage.

11. The LDO of claim 9, wherein the signal is the first control signal.

12. The LDO of claim 9, wherein the signal is obtained from a loading current of the LDO.

13. The LDO of claim 12, wherein the signal is extracted from the loading current of the LDO, and the signal and the loading current of the LDO has a predetermined ratio.

14. The LDO of claim 9, wherein the second switching circuit and the third switching circuit are used to provide a first discharge current and a second discharge current to the output node of the LDO, respectively, and the first discharge current and the second discharge current have different slopes over time axis.

15. The LDO of claim 9, wherein the control circuit comprises:

a transistor, for receiving the comparison result to generate an intermediate signal; and

a logic circuit module, coupled between the transistor and the second switching circuit, for generating the second control signal according to the intermediate signal.

16. The LDO of claim 15, wherein the control circuit further comprises a capacitor coupled between the logic circuit module and the second switching circuit.

17. The LDO of claim 9, further comprising:

a voltage divider, for dividing a voltage at the output node of the LDO to generate the feedback voltage.