Extended utilization area for a memory device

• US 10,540,094 B2
• Filed: 06/13/2016
• Issued: 01/21/2020
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Memory Technologies LLC (Pendrell Corporation)
• Inventors: Hyvonen, Jani, Mylly, Kimmo J., Hakkinen, Jussi, Gyl, Yevgen
• Primary Examiner(s): Choe, Yong J
• Application Number:
  US15/181,293
• Publication Number:
  US 20160357436A1
• Time in Patent Office: 1,317 Days
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Claims

1. A memory device comprising:

two or more predefined access types to determine how access to the memory device is configured for at least one usage of the memory device, wherein the two or more predefined access types correspond to two or more of a sequential write access, a sequential read access, a random write access, and a random read access; and

a controller configured to;

receive, from a host, a command indicative of one or more access needs, the command including a metadata portion for designating at least one of the two or more predefined access types and information for designating at least a portion of the memory device according to the at least one of the two or more predefined access types for the at least one usage; and

configure, based at least in part on the one or more access needs and the information, access to the memory device in accordance with at least one of the two or more predefined access types such that the at least the portion of the memory device is configured according to the at least one of the two or more predefined access types for the at least one usage.

2. The memory device of claim 1, wherein the one or more access needs are received via one or more commands that invoke the at least one of the two or more predefined access types, wherein the one or more commands comprise the command.

3. The memory device of claim 2, wherein the information is first information, and wherein the one or more commands comprise second information settable to invoke the at least one of the two or more predefined access types, the second information comprising one or more bits that have been set, by the host, to invoke the at least one of the two or more predefined access types.

4. The memory device of claim 2, wherein the information comprises one or more bits that have been set, by the host, to designate the at least the portion of the memory device.

5. The memory device of claim 1, wherein the at least the portion of the memory device comprises a number of blocks.

6. The memory device of claim 1, wherein the at least the portion of the memory device comprises a logical portion of the memory device or a physical partition of the memory device.

7. The memory device of claim 1, wherein a first portion of the memory device is configured in accordance with a first access type of the two or more predefined access types and a second portion of the memory device is configured in accordance with a second access type of the two or more predefined access types.

8. A method comprising:

receiving, at a memory device and from a host, one or more commands in accordance with access needs for the memory device to use a first predefined access type of at least the first predefined access type and a second predefined access type, wherein the first predefined access type corresponds to a sequential mode of access, and wherein the one or more commands comprise information designating at least a portion of the memory device according to the first predefined access type for at least one usage; and

configuring, by a controller of the memory device and based at least in part on the one or more commands, access to the memory device in accordance with the first predefined access type such that the at least the portion of the memory device is configured according to the first predefined access type for the at least one usage.

9. The method of claim 8, wherein the information is first information, and wherein the one or more commands further comprise second information settable to activate the first predefined access type, the second information comprising one or more bits that have been set, by the host, to activate the first predefined access type.

10. The method of claim 8, wherein the information comprises one or more bits that have been set, by the host, to designate the at least the portion of the memory device.

11. The method of claim 8, wherein the at least the portion of the memory device comprises a number of blocks.

12. The method of claim 8, wherein the sequential mode of access comprises a sequential write mode.

13. The method of claim 8, wherein the sequential mode of access comprises a sequential read mode.

14. A host device comprising:

an interface to couple the host device to a memory device; and

a controller configured to;

determine at least one mode of access from a plurality of modes of access to be performed in association with the memory device, wherein the plurality of modes of access comprises a sequential mode of access;

set information in one or more commands to designate a portion of the memory device that is to be configured according to a predefined access type associated with the sequential mode of access;

determine that multiple sequential accesses are associated with the portion of the memory device;

send the one or more commands and an indication of one or more access needs from the host device to the memory device that is coupled to the host device, the one or more access needs capable of invoking the predefined access type associated with the sequential mode of access; and

perform the multiple sequential accesses associated with the portion of the memory device.

15. The host device of claim 14, wherein the information is first information, and wherein the controller is further configured to set second information in the one or more commands to indicate the one or more access needs capable of invoking the predefined access type, the second information comprising one or more bits.

16. The host device of claim 14, wherein the information comprises one or more bits.

17. The host device of claim 14, wherein the portion of the memory device comprises a number of blocks.

18. The host device of claim 14, wherein the sequential mode of access comprises a sequential write mode.

19. The host device of claim 14, wherein the sequential mode of access comprises a sequential read mode.

20. A memory device comprising:

one or more access types capable of configuring the memory device for at least one usage, wherein a particular access profile of one or more access profiles corresponds to a sequential read or write mode of access; and

a controller configured to;

receive, from a host, one or more commands that include an access attribute associated with the particular access profile and one or more bits settable, by the host, to designate a portion of the memory device that is configured according to the particular access profile for the at least one usage; and

configure, based at least in part on the one or more commands, the memory device to replace a default access profile with the particular access profile.

21. The memory device of claim 20, wherein the one or more bits are one or more first bits, and wherein the one or more commands comprise:

one or more second bits settable, by the host, to include the access attribute.

22. The memory device of claim 20, wherein the default access profile is pre-selected to accommodate a most likely access need for the memory device.