Nonvolatile logic array based computing over inconsistent power supply

• US 10,541,012 B2
• Filed: 07/25/2017
• Issued: 01/21/2020
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bartling, Steven Craig, Khanna, Sudhanshu
• Primary Examiner(s): Wang, Zhipeng
• Application Number:
  US15/659,111
• Publication Number:
  US 20170323673A1
• Time in Patent Office: 910 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 3/3562 of the master-slave type
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Claims

1. A computing device apparatus comprising:

a processing device comprising;

first, second, and third power domains;

a plurality of non-volatile logic element arrays configured to be powered by the first power domain;

a plurality of volatile storage elements, wherein each volatile storage element includes a retention flip flop circuit having a master latch portion and a slave latch portion, and wherein the master latch portion of each volatile storage element is configured be powered by second power domain and the slave latch portion is configured to be powered by the third power domain; and

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a voltage or current detector configured to sense a power quality from an input power supply;

a power management controller in communication with the voltage or current detector to receive information regarding the power quality and configured to provide to the at least one non-volatile logic controller information effecting storing the machine state to and restoration of the machine state from the plurality of non-volatile logic element arrays;

a voltage regulator connected to receive power from the input power supply and provide power to an output power supply rail configured to provide power to the first, second, and third power domains of the processing device, wherein the voltage regulator is configured to disconnect the output power supply rail from the input power supply in response to a determination that the power quality is below a threshold; and

a charge storage element configured to provide temporary power to the processing device to store the machine state in the plurality of non-volatile logic element arrays after the output power supply rail is disconnected from the input power supply;

wherein;

during the storing of the machine state to the plurality of non-volatile logic element arrays, the first power domain is enabled to power the plurality of non-volatile logic element arrays, the second power domain is enabled to power the master latch portion of each of the plurality of volatile storage elements, and the third power domain is enabled to power the slave latch portion of each of the plurality of volatile storage elements; and

during the restoration of the machine state from the plurality of non-volatile logic element arrays, the first power domain is enabled to power the plurality of non-volatile logic element arrays, the second power domain is disabled to prevent the master latch portion of each of the plurality of volatile storage elements from being powered, and the third power domain is enabled to power the slave latch portion of each of the plurality of volatile storage elements.

2. The computing device apparatus of claim 1, wherein the power management controller is configured to send a signal to effect stoppage of clocks for the processing device in response to the determination that the power quality is below the threshold.

3. The computing device apparatus of claim 1, wherein the voltage regulator is configured to send a disconnect signal to the power management controller in response to disconnecting the output power supply rail from the input power supply.

4. The computing device apparatus of claim 3, wherein the power management controller is configured to send a backup signal to the at least one non-volatile logic controller in response to receiving the disconnect signal.

5. The computing device apparatus of claim 1, wherein the voltage regulator is configured to detect the power quality'"'"'s rising above the threshold and, in response, to send a good power signal to the power management controller.

6. The computing device apparatus of claim 5, wherein the power management controller is configured to send a signal to provide power to the plurality of non-volatile logic element arrays and the at least one non-volatile logic controller to facilitate restoration of the machine state in response to receiving the good power signal.

7. The computing device apparatus of claim 1, wherein the power management controller is configured to determine that power up is complete and, in response, send a signal to effect release of clocks for the processing device, wherein the processing device resumes operation from the machine state prior to the determination that the power quality was below the threshold.

8. The computing device apparatus of claim 1, wherein the charge storage element comprises at least one dedicated on-die capacitor.

9. The computing device apparatus of claim 1, wherein, during storing of the machine state to the plurality of non-volatile logic element arrays, the at least one non-volatile logic controller is configured to enable the first power domain, enable the second power domain, and enable the third power domain.

10. The computing device apparatus of claim 1, wherein, during restoration of the machine state from the plurality of non-volatile logic element arrays, the at least one non-volatile logic controller is configured to enable the first power domain, disable the second power domain, and enable the third power domain.

11. The computing device apparatus of claim 1, wherein the restoration of the machine state from the plurality of non-volatile logic element arrays causes the machine state to be restored into the plurality of volatile storage elements.

12. The computing device apparatus of claim 1, wherein the processing device includes:

a ferroelectric storage device separate from the plurality of non-volatile logic element arrays, the ferroelectric storage device including an array of ferroelectric memory elements; and

a fourth power domain separate from the first, second, and third power domains to supply power to the ferroelectric memory device;

wherein each of the plurality of non-volatile logic elements arrays includes a type of non-volatile storage element that is not a ferroelectric memory element.

13. The computing device apparatus of claim 1, wherein the computing device apparatus is a general purpose processor, a system on a chip (SoC), or a microcontroller.

14. A system comprising:

non-volatile memory;

a plurality of volatile storage elements each including a retention flip flop circuit having a master latch portion and a slave latch portion;

a first power domain configured to power the non-volatile memory;

a second power domain configured to power the master latch portion of each of the volatile storage elements;

a third power domain configured to power the slave latch portion of each of the volatile storage elements;

a non-volatile memory controller configured to control the non-volatile memory to store a machine state represented by the volatile storage elements and to read out a stored machine state from the non-volatile memory to the volatile storage elements;

a detector configured to sense power quality data from an input power supply; and

a power management controller configured to receive the sensed power quality and to provide to the non-volatile controller control information effecting the storing of the machine state to and the restoration of the machine state from the non-volatile memory, the control information being in response to the sensed power quality;

wherein, during the storing of the machine state to the non-volatile memory, the first power domain is enabled to power the non-volatile memory, the second power domain is enabled to power the master latch portion of each of the volatile storage elements, and the third power domain is enabled to power the slave latch portion of each of the volatile storage elements; and

wherein, during the restoration of the machine state from the non-volatile memory, the first power domain is enabled to power the non-volatile memory, the second power domain is disabled to prevent the master latch portion of each of the volatile storage elements from being powered, and the third power domain is enabled to power the slave latch portion of each of the volatile storage elements.

15. The system of claim 14, further comprising a voltage regulator configured to receive power from the input power supply and to provide power to an output power supply rail configured to provide power to the first, second, and third power domains, wherein the voltage regulator is configured to disconnect the output power supply rail from the input power supply in response to a determination that the sensed power quality is below a threshold.

16. The system of claim 15, further comprising a charge storage element configured to provide power for storing the machine state in the non-volatile memory after the output power supply rail is disconnected from the input power supply.