Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory

• US 10,541,015 B2
• Filed: 11/08/2018
• Issued: 01/21/2020
• Est. Priority Date: 05/20/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marotta, Giulio Giuseppe, Tiburzi, Marco Domenico
• Primary Examiner(s): Leboeuf, Jerome
• Application Number:
  US16/184,688
• Publication Number:
  US 20190096464A1
• Time in Patent Office: 439 Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2253 Address circuits or decoders
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.

Claims

1. A virtual ground sensing circuit, comprising:

an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;

a follower circuit including an n-MOS transistor and a p-MOS transistor, an input of the follower circuit including a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit including a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier;

a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential; and

another comparator configured to compare another sense node voltage at a drain of the other of the n-MOS transistor and the p-MOS transistor to another reference voltage potential.

2. The virtual ground sensing circuit of claim 1, wherein a drain of the other of the n-MOS transistor and the p-MOS transistor is operably coupled to a power supply voltage potential.

3. The virtual ground sensing circuit of claim 1, wherein the drain of the one of the n-MOS transistor and the p-MOS transistor is operably coupled to a power supply voltage potential through a transistor configured to isolate the drain of the one of the n-MOS transistor and the p-MOS transistor from the power supply voltage potential during a sense operation.

4. The virtual ground sensing circuit of claim 1, wherein the output of the follower circuit is operably coupled to a conductive line decoder configured to selectively operably couple the output of the follower circuit to one of a plurality of conductive lines of a memory cell array.

5. The virtual ground sensing circuit of claim 1, wherein the comparator is configured to compare a drain voltage potential of the p-MOS transistor to the reference voltage potential.

6. The virtual ground sensing circuit of claim 1, wherein the sense node has a sense node capacitance.

7. The virtual ground sensing circuit of claim 6, wherein the sense node capacitance includes a parasitic capacitance.

8. The virtual ground sensing circuit of claim 1, further comprising one or more other comparators configured to compare the sense node voltage to one or more other reference voltage potentials.

9. The virtual ground sensing circuit of claim 1, further comprising a digital to analog converter (DAC) configured to provide the reference voltage potential to the comparator, wherein a multi-bit digital signal swept from a low digital value to a high digital value is applied to an input of the DAC during a sense operation.

10. The virtual ground sensing circuit of claim 9, further comprising a latch network configured to store a digital value of the multi-bit digital signal that corresponds to a data state of a selected memory cell operably coupled to a conductive line.

11. The virtual ground sensing circuit of claim 10, wherein the latch network is configured to be clocked by an output of the comparator.

12. The virtual ground sensing circuit of claim 1, wherein the operational amplifier is an operational transconductance amplifier.

13. An electrical system, comprising:

at least one memory cell; and

control circuitry operably coupled to the at least one memory cell, the control circuitry comprising;

an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;

a follower circuit comprising an n-MOS transistor and a p-MOS transistor, an input of the follower circuit comprising a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit comprising a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier;

a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential; and

a feedback circuit operably coupling the output of the comparator to the inverting input of the operational amplifier and to a conductive line.

14. The electrical system of claim 13, further comprises the conductive line operably coupled to the at least one memory cell.

15. The electrical system of claim 13, further comprising a digital to analog converter (DAC) configured to receive a digital signal, an output of the DAC operably coupled to an inverting input of the comparator.