Memristive dot product engine for vector processing

• US 10,541,026 B2
• Filed: 03/14/2019
• Issued: 01/21/2020
• Est. Priority Date: 10/29/2014
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Yang, Jianhua, Hu, Miao, Strachan, John Paul, Ge, Ning
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US16/353,451
• Publication Number:
  US 20190214085A1
• Time in Patent Office: 313 Days
• CPC Class Codes: G06F 3/03 Arrangements for converting the position or the displacement of a member into a coded form
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.

Claims

1. A memristive dot product system for vector processing, comprising:

a crossbar array having a number of memory elements, each memory element comprising a transistor and a memristor having more than two conductance levels;

a vector input register; and

a vector output register.

2. The system of claim 1, in which the crossbar array comprises N rows, M columns and N×

M memory elements.

3. The system of claim 2, in which the vector input register comprises N voltage inputs to the crossbar array and the vector output register receives M voltage outputs from the crossbar array.

4. The system of claim 2, in which the N×

M memory elements correspond with values contained in an N×

M matrix.

5. The system of claim 1, further comprising a normally ON depletion mode transistor at each memory element.

6. The memristive dot product system of claim 1, wherein the transistor of each memory element has a plurality of different gate voltages corresponding to the conductance levels.

7. The memristive dot product system of claim 6, wherein the memristor of each memory element is programmable via a plurality of different current levels controlled by the different gate voltages of the transistor of the memory element.

11. The dot-product engine of claim 6, in which the normally ON transistors are depletion mode transistors.

12. The dot-product engine of claim 6, in which the memory elements comprising a jth column of memory locations are linear memristors.

8. A memristive dot-product engine for vector processing, comprising:

a crossbar array comprising a number of memory locations, each memory location comprising a memory element to store information corresponding to a value contained in an N×

M matrix and a transistor to control current flow through the memory element, the transistor receiving a plurality of different gate voltages corresponding to conductance levels of the memory element;

an input register comprising N voltage inputs, each voltage input corresponding to a value contained in a vector having N values; and

an output register comprising M voltage outputs.

9. The dot-product engine of claim 8, wherein the transistors are normally ON transistors.

10. The dot-product engine of claim 9, further comprising M bias voltage wires, in which a jth wire (j=1,M) is connected to the gates of the normally ON transistors comprising a jth column of memory locations.

13. The dot-product engine of claim 8, wherein the conductance levels of the each memory element are greater than two in number.

14. The dot-product engine of claim 13, wherein the memory element of each memory location is programmable via a plurality of different current levels controlled by a corresponding plurality of different gate voltages of the transistor of the memory location.

15. A method for vector-processing using a memristive dot product engine, comprising:

providing a crossbar array comprising M columns, N rows and N×

M memory locations, each memory location comprising a memristor and a transistor, an input register comprising N voltage inputs, and an output register comprising M voltage outputs, the memristor of each memory location programmable via a plurality of different current levels controlled by a corresponding plurality of different gate voltages of the transistor of the memory location;

setting memristance values at the N×

M memory locations within the crossbar array, the memristance values corresponding to row and column values of an N×

M matrix, wherein the memristance value at memory location Ni,Mj is set by applying a programming voltage across the memristor at memory location Ni,Mj;

setting input voltages at the N voltage inputs, the input voltages corresponding to values of an N×

1 vector to be multiplied with the N×

M matrix;

determining output voltages at the M voltage outputs, each output voltage corresponding to the current output at each of the M columns of the crossbar array; and

representing the M×

1 vector result of the multiplication of the N×

M matrix and the N×

1 vector.

16. The method of claim 15, wherein the M voltage outputs are determined by passing current outputs at each of the M columns of the crossbar array through a resistance device.

17. The method of claim 15, wherein the series of steps of setting memristance values at the N×

M memory locations within the crossbar array, setting input voltages at the N voltage inputs, and determining output voltages at the M voltage outputs is performed iteratively until a convergence criteria is satisfied.

18. The method of claim 15, wherein each memory element further comprises a transistor to switch on and off current flow through the memristor.

19. The method of claim 15, wherein the transistor at a memory location Ni,Mj is a normally ON depletion mode transistor.

20. The method of claim 15, wherein the memristor of each memory location has more than two conductance levels, the different gate voltages of the transistor of the memory location corresponding to the conductance levels.