Level-crossing memory trace inspection queries

• US 10,541,042 B2
• Filed: 04/23/2018
• Issued: 01/21/2020
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Nelson, Patrick, Davis, Jackson, Myers, Del, Lai, Thomas, Chen, Deborah, Mola, Jordi, Arevalo Baeza, Juan Carlos
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US15/960,177
• Publication Number:
  US 20190325980A1
• Time in Patent Office: 638 Days
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

Described technologies extend the information available from an execution trace of a program by providing heuristically-derived values for memory contents when the trace does not include data expressly showing the value of a memory cell at a particular execution time. Various heuristics are described. The heuristics may use information about the memory cell at other times to produce the derived value. Some heuristics use other trace data, such as whether the memory cell is in a stack, whether there are gaps in the trace, or whether garbage collection or compilation occurred near the time in question. Grounds for the derived value are reported along with the derived value. A time-travel debugger or other program analysis tool can then present the derived values to users, or make other use of the derived values and grounds to assist debugging and other efforts to improve the functioning of a computing system.

Claims

1. A memory inspection system which provides derived data values from an execution trace, in response to queries from a high-level tool having a data access component (DAC), the memory inspection system comprising:

at least one processor;

a digital memory in operable communication with the processor; and

a DAC adapter which includes a heuristic computation code and an interface, the DAC adapter being configured to, upon execution by the processor, perform a process that includes the following;

(a) receive in the interface a query which specifies a memory cell and an execution time t,

(b) determine automatically that the execution trace fails to expressly specify a known value for the memory cell at the time t,

(c) with the processor, execute the heuristic computation code, whereby the heuristic computation code produces a derived value for the memory cell at the time t based on information in the execution trace, and

(d) provide in the interface a response to the query, the response including the derived value together with an indication that the value provided in the response for the memory cell at the time t is derived, inclusion of the derived value based at least upon uncertainty as to the value of the memory cell at time tin view of the execution trace.

2. The memory inspection system of claim 1, wherein the heuristic computation code comprises a single-bracketing-value heuristic computation code which is configured to upon execution:

identify in the execution trace a value v for the memory cell at an execution time tp,

identify in the execution trace the same value v for the memory cell at an execution time tf, and

produce v as the derived value for the memory cell at the time t.

3. The memory inspection system of claim 1, wherein the heuristic computation code comprises a prefer-closer-in-time heuristic computation code which is configured to upon execution perform at least one of the following:

identify in the execution trace a value vm for the memory cell at an execution time t−

m, identify in the execution trace a value vn for the memory cell at an execution time t−

n, where m>

n>

0, and produce vn as the derived value for the memory cell at the time t;

or

identify in the execution trace a value vm for the memory cell at an execution time t+m, identify in the execution trace a value vn for the memory cell at an execution time t+n, where m>

n>

0, and produce vn as the derived value for the memory cell at the time t.

4. The memory inspection system of claim 1, wherein the heuristic computation code comprises a prefer-past heuristic computation code which is configured to upon execution:

identify in the execution trace a value vp for the memory cell at an execution time tp,

identify in the execution trace a value of for the memory cell at an execution time tf, and

produce vp as the derived value for the memory cell at the time t.

5. The memory inspection system of claim 1, wherein the heuristic computation code comprises a stack-memory heuristic computation code which is configured to upon execution:

identify in the execution trace a value v for the memory cell at an execution time tp,

determine stack memory activity between tp and an execution time t, including determining that the memory cell was part of allocated stack memory at tp and determining whether stack shrinkage excluded the memory cell from allocated stack memory between tp and t, and

produce v as the derived value for the memory cell at the time t together with a ground indicating the stack memory activity determined.

6. The memory inspection system of claim 1, wherein the heuristic computation code comprises an external-access-likelihood heuristic computation code which is configured to upon execution:

identify in the execution trace a value vp for a memory cell at an execution time tp of a thread,

obtain an access likelihood estimate based on a characteristic of the memory cell and indicating a likelihood that the memory cell was written by a code external to the thread, and

produce vp as the derived value for the memory cell at the time t and with vp produce a ground indicating the characteristic of the memory cell and use of that characteristic in producing vp.

7. The memory inspection system of claim 1, wherein the heuristic computation code comprises a prefer-no-gap heuristic computation code which is configured to upon execution:

identify in the execution trace a value vj for the memory cell at an execution time tj, with tj prior to t,

identify in the execution trace a value vk for the memory cell at an execution time tk, with tk prior to t,

determine that there is a tracing gap in the trace such that tracing did not occur for at least part of an interval between the times tj and t,

determine that there is no tracing gap in the trace between the times tk and t, and

produce vk as the derived value for the memory cell at the time t.

8. The memory inspection system of claim 1, wherein the heuristic computation code comprises a prefer-current-thread heuristic computation code which is configured to upon execution:

identify in the execution trace a value vc for the memory cell at an execution time tc on a thread tcurr which was executing at time t,

identify in the execution trace a value vd for the memory cell at a different execution time td on a thread tdiff which is a different thread than tcurr, and

produce vc as the derived value for the memory cell at the time t based at least in part on tcurr being the thread which was executing at time t.

9. A computer-implemented memory inspection process which provides derived data values of memory cells from an execution trace, the memory inspection process comprising:

receiving a query which specifies a plurality of memory cells and an execution time t;

with a computer processor, executing a heuristic computation which searches at least a portion of the execution trace for state information of the memory cells;

obtaining as results of the heuristic computation a respective derived value of each memory cell and a respective ground of that derived value, the obtained grounds comprising at least two of the following grounds;

known-past-value, known-current-value, known-future-value; and

reporting the derived values of the memory cells, together with at least one of the grounds, in a response to the query;

wherein the reporting comprises providing information about the value of the memory cells which is not limited to any values that were recorded into the execution trace at time t, and the derived values are based at least in part upon uncertainty as to the value of one or more of the memory cells at time tin view of the execution trace.

10. The memory inspection process of claim 9, further comprising blending the obtained grounds into a blended ground, and wherein the reporting comprises reporting the derived values of the memory cells together with the blended ground.

11. The memory inspection process of claim 10, wherein blending the obtained grounds comprises selecting as the blended ground a most pessimistic ground, and wherein the selecting is based at least in part on a ranking which ranks grounds as follows from most pessimistic to least pessimistic:

no-value-found, known-future-value, known-past-value, known-current-value.

12. The memory inspection process of claim 9, wherein the process comprises:

receiving a query which specifies a memory cell A and a memory cell B and an execution time t;

identifying in the trace at least the following while executing the heuristic computation;

a value vAp for memory cell A at an execution time t−

p, a value vAf for memory cell A at an execution time t+f, and a value vB for memory cell B at the time t−

p and also at the time t+f, where p>

0, f>

0, and vAf is not equal to vAp; and

producing vAp as the derived value of the memory cell A, and producing vB as the derived value of the memory cell B, in a response to the query,

thereby applying a heuristic which is denoted here a prefer-values-registered-together heuristic.

13. A computer readable storage medium configured with code which upon execution by a computer processor performs a trace-based memory inspection process, the process comprising:

receiving a query which specifies a memory cell and an execution time t;

with the computer processor, determining that an execution trace fails to expressly specify a known value for the memory cell at the time t;

with the computer processor, executing a heuristic computation which searches at least a portion of the execution trace for state information of the memory cell;

obtaining as results of the heuristic computation a derived value of the memory cell and a ground of that derived value; and

reporting the derived value of the memory cell, together with the ground, in a response to the query;

wherein the reporting comprises providing information about the value of the memory cell which is not limited to any values that were recorded into the execution trace at time t, and the derived values are based at least in part upon uncertainty as to the value of one or more of the memory cells at time tin view of the execution trace.

14. The computer readable storage medium of claim 13, wherein executing the heuristic computation comprises:

identifying in the trace a write operation which wrote a value vf to the memory cell at an execution time tf, with tf after an execution time t, and

producing vf in the heuristic computation results as the derived value of the memory cell at the execution time t,

thereby applying a heuristic which is denoted here a use-future-write heuristic.

15. The computer readable storage medium of claim 13, wherein the query specifies a memory cell which is allocated to hold a property value, and the property value is defined by a calculation which is configured to read at least one other memory cell to obtain a value x for use in calculating the property value, and wherein the process comprises executing at least one heuristic computation to obtain a derived value for x.

16. The computer readable storage medium of claim 13, wherein the process comprises:

performing multiple executions of one or more heuristic computations which search at least a portion of the execution trace for state information; and

building a map between execution time t and multiple memory cells using one or more of the following;

one or more values recorded at time t in the execution trace, one or more derived values produced by the one or more heuristic computations.

17. The computer readable storage medium of claim 13, wherein executing the heuristic computation comprises:

identifying in the trace a value vbgc for the memory cell at an execution time tb,

identifying in the trace a value vagc for the memory cell at an execution time ta,

identifying in the trace a time tgc at which a compacting garbage collection operation began, where tb is prior to tgc and tgc is prior to ta, and

producing vbgc in the heuristic computation results as the derived value of the memory cell and based at least on a capacity of the garbage collection operation to alter the value of the memory cell,

thereby applying a heuristic which is denoted here a before-garbage-collection heuristic.

18. The computer readable storage medium of claim 13, wherein executing the heuristic computation comprises:

identifying in the trace a value vbjit for the memory cell at an execution time tb,

identifying in the trace a value vajit for the memory cell at an execution time ta,

identifying in the trace a time tjit at which a just-in-time or dynamic compilation operation began, where tb is prior to tjit and tjit is prior to ta, and

producing vbjit in the heuristic computation results as the derived value of the memory cell and based at least on a capacity of the just-in-time or dynamic compilation operation to alter the value of the memory cell,

thereby applying a heuristic which is denoted here a before-jit-compilation heuristic.

19. The computer readable storage medium of claim 13, wherein executing the heuristic computation comprises:

identifying in the trace a value vp for the memory cell at an execution time t−

p, with p>

0,

identifying in the trace a value vf for the memory cell at an execution time t+f, with f>

0, selecting a delta value d,

when (t+d>

t+f) and (t−

d>

t−

p) then producing vf in the heuristic computation results as the derived value of the memory cell, and otherwise producing vp as the derived value of the memory cell,

thereby applying a heuristic which is denoted here a prefer-close-future-else-past heuristic.

20. The computer readable storage medium of claim 13, wherein

executing the heuristic computation comprises applying at least one of the following heuristics:

a single-bracketing-value heuristic;

a prefer-closer-in-time heuristic;

a prefer-past heuristic;

a stack-memory heuristic;

an access-likelihood heuristic;

a prefer-no-gap heuristic;

a prefer-current-thread heuristic;

a prefer-values-registered-together heuristic;

a use-future-write heuristic;

a before-garbage-collection heuristic;

a before-jit-compilation heuristic;

or

a prefer-close-future-else-past heuristic.