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3D flash memory cells which discourage cross-cell electrical tunneling

  • US 10,541,246 B2
  • Filed: 04/30/2018
  • Issued: 01/21/2020
  • Est. Priority Date: 06/26/2017
  • Status: Active Grant
First Claim
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1. A 3-d flash memory cell, the 3-d flash memory cell comprising:

  • a stack of silicon oxide slabs, wherein a tungsten slab selected from a plurality of tungsten slabs is disposed between each neighboring pair of vertically neighboring silicon oxide slabs in a memory hole of the 3-d flash memory cell, wherein the plurality of tungsten slabs are recessed relative to the silicon oxide slabs away from the memory hole to form a plurality of recesses;

    a plurality of compound floating gates each comprising a polysilicon buffer portion and a high work function metal portion, wherein the plurality of compound floating gates are disposed entirely within the plurality of recesses, wherein the stack of silicon oxide slabs extends beyond the plurality of compound floating gates into the memory hole; and

    a high-k dielectric liner disposed between the stack of silicon oxide slabs and the plurality of tungsten slabs, wherein the high-k dielectric liner is further disposed between the plurality of compound floating gates and the tungsten slabs, and wherein the high-k dielectric liner comprises aluminum oxide.

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