Image sensor package having multi-level stack structure

• US 10,541,263 B2
• Filed: 10/30/2017
• Issued: 01/21/2020
• Est. Priority Date: 11/14/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-hoon, Kim, Ji-chul, Cha, Seung-yong, Kim, Jae-choon
• Primary Examiner(s): Ojeh, Nduka E
• Application Number:
  US15/797,375
• Publication Number:
  US 20180138225A1
• Time in Patent Office: 813 Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Claims

1. An image sensor package, comprising:

an image sensor chip mounted above a package substrate and including a pixel array and an interconnection structure, the image sensor chip to receive a power voltage, a ground voltage, or signals;

a logic chip vertically overlapping the image sensor chip above the package substrate, the logic chip including a logic substrate and at least one first through silicon via (TSV) contact passing through the logic substrate, and the logic chip to process a pixel signal output by the image sensor chip and to receive the power voltage, the ground voltage, or the signals via the image sensor chip; and

a memory chip structure vertically overlapping the image sensor chip and the logic chip above the package substrate, the memory chip structure including;

a memory chip,

a molding portion surrounding the memory chip, and

at least one through mold via (TMV) contact vertically passing through an entire thickness of the molding portion and connected to at least one of the logic chip or the memory chip, the at least one TMV contact of the memory chip structure being aligned with the at least one first TSV contact of the logic chip,

wherein the memory chip is to store at least one of a pixel signal processed by the logic chip or a pixel signal output by the image sensor chip and to receive the power voltage, the ground voltage, or the signals via the image sensor chip and the logic chip,

wherein the image sensor chip further includes an additional TSV contact, the at least one first TSV contact of the logic chip being aligned with and connected to the additional TSV contact of the image sensor chip.

2. The image sensor package as claimed in claim 1, further comprising:

at least one redistribution structure in at least one of the logic chip or the memory chip structure, wherein the logic chip is to receive the power voltage, the ground voltage, or the signals via the image sensor chip and the at least one redistribution structure.

3. The image sensor package as claimed in claim 1, wherein:

the logic chip further includes an interconnection structure on the logic substrate, the at least one first TSV contact passing through the logic substrate and the interconnection structure,

and

the memory chip is to receive the power voltage, the ground voltage, or the signals via the image sensor chip and the first TSV contact.

4. The image sensor package as claimed in claim 3, wherein:

the logic chip further includes a second TSV contact passing through the logic substrate and having an end connected to an interconnection layer in the interconnection structure of the logic chip, and a logic redistribution structure connected to the at least one first TSV contact and the second TSV contact, and

the logic chip is to receive the power voltage, the ground voltage, or the signals via the image sensor chip, the first TSV contact, the logic redistribution structure, and the second TSV contact in this stated order.

5. The image sensor package as claimed in claim 1, further comprising:

at least one redistribution structure in at least one of the logic chip or the memory chip structure, wherein the at least one redistribution structure includes at least one heater portion to provide heat only to a portion of the pixel array depending on applied power.

6. The image sensor package as claimed in claim 1, further comprising:

at least one redistribution structure in at least one of the logic chip or the memory chip structure, wherein the at least one redistribution structure includes;

a conductive line connected to an internal circuit of at least one of the logic chip or the memory chip, and

a heater line connected to neither the internal circuit of the logic chip nor the internal circuit of the memory chip, the heater line including at least one heater portion to provide heat only to a portion of the pixel array depending on applied power.

7. The image sensor package as claimed in claim 1, wherein:

the memory chip structure includes a memory redistribution structure extending between the memory chip and the logic chip and between the molding portion and the logic chip, the memory redistribution structure connected to an interconnection structure within the memory chip, and

the memory redistribution structure includes;

an insulating layer covering the memory chip and the molding portion, and

a plurality of memory redistribution lines on the insulating layer, portions of the plurality of memory redistribution lines extending through the insulating layer to contact a top surface of the memory chip and a top surface of the at least one TMV contact.

8. An image sensor package, comprising:

an image sensor chip mounted above a package substrate and including a pixel array and an interconnection structure;

a logic chip vertically overlapping the image sensor chip above the package substrate, the logic chip to process a pixel signal output by the image sensor chip;

a memory chip structure vertically overlapping the image sensor chip and the logic chip above the package substrate, the memory chip structure including;

a memory chip,

a molding portion surrounding the memory chip, and

at least one through molding via (TMV) contact vertically passing through the molding portion and connected to at least one of the logic chip or the memory chip;

at least one redistribution structure in at least one of the logic chip or the memory chip structure, the at least one redistribution structure including a plurality of memory redistribution lines on an insulating layer, and portions of the plurality of memory redistribution lines extending through the insulating layer to contact a top surface of the memory chip and a top surface of the at least one TMV contact; and

a through silicon via (TSV) contact passing through the logic chip and having a first end connected to the interconnection structure of the image sensor chip and a second end connected to the at least one redistribution structure, the at least one TMV contact of the memory chip structure being aligned with the TSV contact,

wherein the memory chip is to store at least one of a pixel signal processed by the logic chip or a pixel signal output by the image sensor chip and wherein the memory chip is connected to the logic chip via the at least one redistribution structure and is connected to the image sensor chip via the at least one redistribution structure and the TSV contact.

9. The image sensor package as claimed in claim 8, wherein the logic chip is between the memory chip structure and the image sensor chip.

10. The image sensor package as claimed in claim 8, wherein:

the molding portion extends continuously on an entire sidewall of the memory chip, the molding portion being between the package substrate and a bottom of the at least one redistribution structure, and

the at least one TMV contact includes;

a first TMV contact extending vertically with respect to the package substrate through an entire thickness of the molding portion, the first TMV contact being connected to at least one of the logic chip or the memory chip via the at least one redistribution structure, and

a second TMV contact extending vertically with respect to the package substrate through an entire thickness of the molding portion, the second TMV contact being aligned with the TSV contact and being connected to the image sensor chip via the TSV contact, and top surfaces of the first TMV, second TMV, and memory chip being substantially level.

11. The image sensor package as claimed in claim 8, wherein the at least one redistribution structure includes at least one heater line including a heater portion.

12. The image sensor package as claimed in claim 8, wherein the at least one redistribution structure includes:

a memory redistribution structure covering the memory chip and the molding portion on a surface of the memory chip structure facing the logic chip, the memory redistribution structure including a plurality of memory redistribution lines selectively connected to an interconnection structure in the memory chip and the at least one TMV contact, and

a logic redistribution structure on a surface of the logic chip facing the memory chip structure, the logic redistribution structure including a plurality of logic redistribution lines connected to an interconnection structure in the logic chip, wherein the memory redistribution structure and the logic redistribution structure are spaced apart from each other and are in parallel.

13. The image sensor package as claimed in claim 12, wherein the second end of the TSV contact is connected to an internal circuit of the logic chip via at least one of the logic redistribution structure or the memory redistribution structure.

14. The image sensor package as claimed in claim 12, wherein the second end of the TSV contact is connected to an internal circuit of the memory chip via at least one of the logic redistribution structure or the memory redistribution structure.

15. The image sensor package as claimed in claim 12, wherein at least one of the memory redistribution structure or the logic redistribution structure includes at least one heater line including a heater portion.