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Image sensor package having multi-level stack structure

  • US 10,541,263 B2
  • Filed: 10/30/2017
  • Issued: 01/21/2020
  • Est. Priority Date: 11/14/2016
  • Status: Active Grant
First Claim
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1. An image sensor package, comprising:

  • an image sensor chip mounted above a package substrate and including a pixel array and an interconnection structure, the image sensor chip to receive a power voltage, a ground voltage, or signals;

    a logic chip vertically overlapping the image sensor chip above the package substrate, the logic chip including a logic substrate and at least one first through silicon via (TSV) contact passing through the logic substrate, and the logic chip to process a pixel signal output by the image sensor chip and to receive the power voltage, the ground voltage, or the signals via the image sensor chip; and

    a memory chip structure vertically overlapping the image sensor chip and the logic chip above the package substrate, the memory chip structure including;

    a memory chip,a molding portion surrounding the memory chip, andat least one through mold via (TMV) contact vertically passing through an entire thickness of the molding portion and connected to at least one of the logic chip or the memory chip, the at least one TMV contact of the memory chip structure being aligned with the at least one first TSV contact of the logic chip,wherein the memory chip is to store at least one of a pixel signal processed by the logic chip or a pixel signal output by the image sensor chip and to receive the power voltage, the ground voltage, or the signals via the image sensor chip and the logic chip,wherein the image sensor chip further includes an additional TSV contact, the at least one first TSV contact of the logic chip being aligned with and connected to the additional TSV contact of the image sensor chip.

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