Semiconductor device and method of making thereof

• US 10,541,300 B2
• Filed: 05/26/2016
• Issued: 01/21/2020
• Est. Priority Date: 05/26/2016
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Losee, Peter Almern, Bolotnikov, Alexander Viktorovich, Sui, Yang
• Primary Examiner(s): Gauthier, Steven B
• Application Number:
  US15/164,928
• Publication Number:
  US 20170345890A1
• Time in Patent Office: 1,335 Days
• Field of Search: None
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

Claims

1. A silicon carbide (SiC) field effect transistor (FET) comprising:

a first layer having a first conductivity type that forms a drift region of the SiC FET;

a second layer disposed directly atop the first layer, the second layer having the first conductivity type;

a laterally graded and segmented termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and

an active region at least partially formed in the second layer, wherein the active region comprises second layer dopant concentration that increases by at least five (5) times from a surface of the active region to a depth at which a peak dopant concentration is disposed, wherein the active region comprises a well region that is contiguous with a first lateral side of the termination region, and wherein the second layer is contiguous with a second lateral side of the termination region opposite the first side.

2. The SiC FET of claim 1, wherein an average dopant concentration of the second layer is greater than an average dopant concentration of the first layer.

3. The SiC FET of claim 1, where the second layer extends entirely across the first layer of the SiC FET.

4. The SiC FET of claim 1, wherein the well region of the active region comprises a body region.

5. The SiC FET of claim 1, wherein a substrate disposed beneath the first layer comprises silicon carbide (SiC).

6. The SiC FET of claim 1, wherein an average dopant concentration of the second layer is between about two (2) times to about fifteen (15) times greater than that of the first layer.

7. The SiC FET of claim 1, wherein a dopant concentration profile within the second layer as measured from a surface of the second layer to a first depth of the second layer comprises a retrograde profile.

8. The SiC FET of claim 7, wherein an average dopant concentration at a depth of at least 0.2 μ

m from a surface of the second layer is at least four (4) times greater than that of an average dopant concentration at the surface of the second layer.

9. The SiC FET of claim 7, wherein an average dopant concentration at the surface of the second layer is up to about 1×

10¹⁶ cm<sup>−

3</sup>.

10. The SiC FET of claim 7, wherein a sheet doping concentration of dopants within an area defined as between the surface of the second layer to a depth of about 1.5 μ

m is between about 2×

10¹² cm<sup>−

2</sup> to about 5×

10¹² cm<sup>−

2</sup>.

11. The SiC FET of claim 7, wherein a dopant concentration of the second layer is less than about 20% of a dopant concentration of the well region of the active area at substantially similar depths into the second layer and well region until a depth of about 0.15 um to 0.3 um from the surface of the second layer.

12. The SiC FET of claim 7, wherein a dopant concentration profile of a sheet doping concentration within the termination region as measured from a surface of the termination region to the first depth of the termination region comprises a retrograde profile or a box-like profile, and wherein a peak dopant concentration of the termination region is greater than a peak dopant concentration of the second layer.

13. The SiC FET of claim 1, wherein the termination region comprises one or more of a segmented termination region, a multi-zoned junction termination extension, a continuous junction termination extension, and one or more guard rings.

14. The SiC FET of claim 1, wherein the first layer is a first SiC epitaxial (epi) layer and the second layer is a second SiC epi layer disposed directly atop the first SiC epi layer.

15. The SiC FET of claim 1, wherein the first layer is a first SiC epitaxial (epi) layer and the second layer is a doped region disposed directly adjacent to a top surface of the first SiC epi layer.

16. A field effect transistor (FET) semiconductor device, comprising:

a first layer having a first conductivity type that forms a drift region of the FET semiconductor device;

a second layer disposed directly atop the first layer, the second layer having the first conductivity type, wherein a dopant concentration profile of an average dopant concentration within the second layer as measured from a surface of the second layer to a first depth of the second layer comprises a retrograde profile;

a laterally graded and segmented termination region formed in the second layer, the termination region having a second conductivity type opposite the first type, wherein the average dopant concentration of the second layer is greater than an average dopant concentration of the first layer; and

an active region at least partially formed in the second layer, wherein the active region comprises a well region that is contiguous with a first lateral side of the termination region and wherein the second layer is contiguous with a second lateral side of the termination region opposite the first side.

17. The FET semiconductor device of claim 16, wherein the first layer, the second layer, and a substrate disposed beneath the first layer comprises silicon carbide (SiC).

18. The FET semiconductor device of claim 16, wherein the average dopant concentration at a depth of at least 0.2 um from the surface of the second layer is at least four (4) times greater than that of an average dopant concentration at the surface of the second layer.

19. The FET semiconductor device of claim 16, wherein the average dopant concentration at the surface of the second layer is up to about 1×

10¹⁶ cm<sup>−

3</sup>.

20. The FET semiconductor device of claim 16, wherein a sheet doping concentration of dopants within an area defined as between the surface of second layer to a depth of about 1.5 μ

m is between about 2×

10¹² cm<sup>−

2</sup> to about 5×

10¹² cm<sup>−

2</sup>.

21. The FET semiconductor device of claim 16, wherein a dopant concentration of the second layer is less than about 20% of a dopant concentration of a well region formed in the active region at substantially similar depths into the second layer and well region until a depth of about 0.15 um to 0.3 um from the surface of the second layer.

22. The FET semiconductor device of claim 16, wherein a dopant concentration profile of an average dopant concentration within the termination region as measured from a surface of the termination region to a second depth of the termination region comprises a retrograde profile or a box-like profile, and wherein a peak dopant concentration of the termination region is greater than a peak dopant concentration of the second layer.

23. The FET semiconductor device of claim 16, wherein the active region comprises a dopant concentration that increases by at least five (5) times from a surface of the active region to a depth at which a peak concentration is disposed.

24. A silicon carbide (SiC) field effect transistor (FET) device comprising:

a first layer having a first conductivity type that forms a drift region of the SiC FET device;

a second layer disposed directly atop the first layer, the second layer having the first conductivity type, wherein a dopant concentration profile of an average dopant concentration within the second layer as measured from a surface of the second layer to a first depth of the second layer comprises a retrograde profile;

a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and

an active region at least partially formed in the second layer, wherein the active region comprises a well region that is contiguous with a first lateral side of the termination region, and wherein the second layer is contiguous with a second lateral side of the termination region opposite the first side.

25. The FET device of claim 24, wherein the active region comprises second layer dopant concentration that increases by at least five (5) times from a surface of the active region to a depth at which a peak dopant concentration is disposed.

26. The FET device of claim 24, wherein an average dopant concentration of the second layer is between about two (2) times to about fifteen (15) times greater than that of the first layer.

27. The FET device of claim 24, wherein the termination region comprises a laterally graded and segmented termination region.

28. The FET device of claim 24, wherein the average dopant concentration at a depth of at least 0.2 μ

m from the surface of the second layer is at least four (4) times greater than that of an average dopant concentration at the surface of the second layer.