Granular dynamic test systems and methods

• US 10,545,189 B2
• Filed: 10/27/2016
• Issued: 01/28/2020
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sonawane, Milind, Sanghani, Amit, Colburn, Jonathon E., Nelapatla, Bala Tarun, Sarangi, Shantanu, Kumar reddy.S, Rajendra, Chadalavada, Sailendra
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/336,716
• Publication Number:
  US 20170115353A1
• Time in Patent Office: 1,188 Days
• Field of Search: 714727, 714726, 714729, 714731
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

Claims

1. A system comprising:

a plurality of scan test chains configured to perform test operations on components in a circuit partition, wherein the scan test chains perform the test operations at a first clock speed;

a central test controller for controlling the test operations by the scan test chains; and

an interface configured to generate instructions that direct the central test controller, wherein the interface communicates with the central test controller at the first clock speed and an external scan input at a second clock speed, wherein the second clock speed is a faster frequency than the first clock speed.

2. The system of claim 1, wherein the first clock speed is a faster frequency than a test access port (TAP) clock (CLK) speed.

3. The system of claim 1, wherein the instructions that direct the central test controller includes directions associated with sequential scan compression/decompression operations.

4. The system of claim 1, wherein the instructions that direct the central test controller includes directions associated with combinational scan compression/decompression operations.

5. The system of claim 1, wherein the interface further comprises a mode state machine used to generate test mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

6. The system of claim 1, wherein the interface operations are coordinated with a dynamic standard test access (DSTA) operation associated with test data input and test data output.

7. The system of claim 6, wherein the dynamic standard test access is coordinated with the second clock speed for communication of external data and the first clock speed for communication of internal data.

8. A test method comprising

receiving external test information at an external communication rate;

converting the external test information into control instructions for a central test controller; and

communicating the control instructions to the central test controller in accordance with an internal communication rate, wherein the external communication rate is different than the internal communication rate, wherein a difference in the external communication rate and the internal communication rate is coordinated to compensate for differences between deserialization of the external test information and serialization of the control instructions.

9. The method of claim 8 wherein the external communication rate is a faster frequency than the internal communication rate.

10. The method of claim 8 wherein the converting comprises generating state instructions for the central test controller.

11. The method of claim 8 wherein the converting comprises generating mode instructions for the central test controller.

12. The method of claim 8 further comprising deserializing the external test information in which a single stream of the external test information is received at an external communication rate and a plurality of streams are forwarded at the internal communication rate.

13. The method of claim 8 wherein the control instructions are compatible with a type of testing and the type of testing is selected from the group comprising Automatic Test Pattern Generation (ATPG) testing, Memory Built In Self Test (MBIST), and Input/Output Built In Self Test (IOBIST).

14. The method of claim 8 wherein the converting is compatible with concurrent testing of multiple independent test partitions.

15. A system comprising:

a plurality of functional components arranged in physical partitions;

a plurality of scan test chains configured to perform test operations on the plurality of functional components at a first clock speed;

a centralized test controller for controlling testing by the scan test chains; and

an interface configured to communicate with the centralized test controller via external scan inputs at a second clock speed, wherein the second clock speed is a faster frequency than the first clock speed, wherein a difference in the first clock speed and the second clock is coordinated to compensate for deserialization of the external test information.

16. The system of claim 15 wherein:

each partition has a sequential compressor and de-compressor;

test data input has a corresponding deserializer; and

test data output has a corresponding serializer.

17. The system of claim 15 wherein the interface facilitates independent management of the testing of the functional components.

18. The system of claim 17 wherein the interface facilitates concurrent testing across the physical partitions.

19. The system of claim 17 wherein the interface facilitates different types of testing across the physical partitions.

20. The system of claim 15 wherein the interface is a standardized test interface.

21. An interface device comprising:

a mode state machine configured to derive test mode control signals forwarded to a test partition central controller; and

a test register state machine configured to derive test state control signals forwarded to the test partition central controller, and

a deserializer that deserializes a stream of test related information from an external source into a mode state machine input and a test register state machine input, wherein a first input side of the deserializer receives test information communicated via an external communication port and a second output side of the deserializer forwards test information to the mode state machine and the test register state machine, wherein the first input side of the deserializer operates at a first clock rate and the second output side of the deserializer operates at a second clock rate, wherein the first clock rated is a faster frequency than the second clock rate.

22. The interface device of claim 21, wherein the test partition central controller is configured to coordinate test control information for test scan compression components and test scan decompression components.

23. The interface device of claim 21, wherein the test register state machine is driven by a data load serialize/deserialize component.

24. The interface device of claim 21, wherein the data load serialize/deserialize module is included in a dynamic standard test access (DTSA) component.

25. The interface device of claim 21, wherein the mode state machine and the test register state machine are in lock state.