Granular dynamic test systems and methods
First Claim
1. A system comprising:
- a plurality of scan test chains configured to perform test operations on components in a circuit partition, wherein the scan test chains perform the test operations at a first clock speed;
a central test controller for controlling the test operations by the scan test chains; and
an interface configured to generate instructions that direct the central test controller, wherein the interface communicates with the central test controller at the first clock speed and an external scan input at a second clock speed, wherein the second clock speed is a faster frequency than the first clock speed.
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Accused Products
Abstract
In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.
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Citations
25 Claims
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1. A system comprising:
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a plurality of scan test chains configured to perform test operations on components in a circuit partition, wherein the scan test chains perform the test operations at a first clock speed; a central test controller for controlling the test operations by the scan test chains; and an interface configured to generate instructions that direct the central test controller, wherein the interface communicates with the central test controller at the first clock speed and an external scan input at a second clock speed, wherein the second clock speed is a faster frequency than the first clock speed. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A test method comprising
receiving external test information at an external communication rate; -
converting the external test information into control instructions for a central test controller; and communicating the control instructions to the central test controller in accordance with an internal communication rate, wherein the external communication rate is different than the internal communication rate, wherein a difference in the external communication rate and the internal communication rate is coordinated to compensate for differences between deserialization of the external test information and serialization of the control instructions. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a plurality of functional components arranged in physical partitions; a plurality of scan test chains configured to perform test operations on the plurality of functional components at a first clock speed; a centralized test controller for controlling testing by the scan test chains; and an interface configured to communicate with the centralized test controller via external scan inputs at a second clock speed, wherein the second clock speed is a faster frequency than the first clock speed, wherein a difference in the first clock speed and the second clock is coordinated to compensate for deserialization of the external test information. - View Dependent Claims (16, 17, 18, 19, 20)
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21. An interface device comprising:
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a mode state machine configured to derive test mode control signals forwarded to a test partition central controller; and a test register state machine configured to derive test state control signals forwarded to the test partition central controller, and a deserializer that deserializes a stream of test related information from an external source into a mode state machine input and a test register state machine input, wherein a first input side of the deserializer receives test information communicated via an external communication port and a second output side of the deserializer forwards test information to the mode state machine and the test register state machine, wherein the first input side of the deserializer operates at a first clock rate and the second output side of the deserializer operates at a second clock rate, wherein the first clock rated is a faster frequency than the second clock rate. - View Dependent Claims (22, 23, 24, 25)
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Specification