Electronic device and method for operating the same
First Claim
1. An electronic device capable of placing restrictions on processor usage, comprising:
- a memory; and
a processor comprising a first core and a second core,wherein the memory includes stored instructions that, when executed by the processor cause;
control the first core to transit from an online state to an idle state in response to a restriction signal for the first core, wherein the idle state is a state in which power lower than power supplied in the online state is supplied to the first core,control the first core to transit to a power save state when the first core remains in the idle state for at least a preset time, wherein the power save state is a state in which power lower than power supplied in the idle state is supplied to the first core,cause the first core to perform blocking an interrupt request signal sent to the first core enabling the first core to continuously remain in the idle state, andwherein the interrupt request signal comprises the interrupt request signal sent by the second core to all cores including the first core.
1 Assignment
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Accused Products
Abstract
An electronic device capable of placing restrictions on processor usage is disclosed. The electronic device may include: a memory; and a processor including a first core and a second core. The memory may store instructions that, when executed by the processor, cause the first core to transition from an active state to an idle state in response to a restriction signal for the first core, and cause the first core to transition to a power save state when the first core remains in the idle state for at least a preset time. For hot-unplugging, as the electronic device does not transition a core to an offline state, it does not have to perform cleanup operation on the memory and variables. Hence, it is possible to reduce the latency time due to hot-unplugging.
11 Citations
17 Claims
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1. An electronic device capable of placing restrictions on processor usage, comprising:
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a memory; and a processor comprising a first core and a second core, wherein the memory includes stored instructions that, when executed by the processor cause; control the first core to transit from an online state to an idle state in response to a restriction signal for the first core, wherein the idle state is a state in which power lower than power supplied in the online state is supplied to the first core, control the first core to transit to a power save state when the first core remains in the idle state for at least a preset time, wherein the power save state is a state in which power lower than power supplied in the idle state is supplied to the first core, cause the first core to perform blocking an interrupt request signal sent to the first core enabling the first core to continuously remain in the idle state, and wherein the interrupt request signal comprises the interrupt request signal sent by the second core to all cores including the first core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of operating an electronic device capable of placing restrictions on the usage of a processor including a first core and a second core, the method comprising:
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causing the first core to transition from an online state to an idle state in response to a restriction signal for the first core, wherein the idle state is a state in which power lower than power supplied in the online state is supplied to the first core; causing the first core to transition to a power save state when the first core remains in the idle state for at least a preset time, wherein the power save state is a state in which power lower than power supplied in the idle state is supplied to the first core, causing the first core to perform blocking an interrupt request signal sent to the first core enabling the first core to continuously remain in the idle state, and wherein the interrupt request signal comprises the interrupt request signal sent by the second core to all cores including the first core. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification