Dynamic thread status retrieval using inter-thread communication

• US 10,545,797 B2
• Filed: 02/08/2016
• Issued: 01/28/2020
• Est. Priority Date: 02/14/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuesel, Jamie R., Kupferschmidt, Mark G., Schardt, Paul E., Shearer, Robert A.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Nguyen, William V
• Application Number:
  US15/018,190
• Publication Number:
  US 20160154683A1
• Time in Patent Office: 1,450 Days
• CPC Class Codes: G06F 11/30 Monitoring
• CPC Class Codes: G06F 11/3031 where the computing system component is a motherboard or an expansion card
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3072 where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting
• CPC Class Codes: G06F 11/3096 wherein the means or processing minimize the use of computing system or of computing system component resources, e.g. non-intrusive monitoring which minimizes the probe effect: sniffing, intercepting, indirectly deriving the monitored data from other directly available data
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

A method for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread without interrupting processing of the slave hardware thread/hardware resource.

Claims

1. A method for retrieving a status for a slave hardware thread in a network on a chip (NOC) processing system comprising a plurality of hardware threads configured in a plurality of interconnected integrated processor blocks implemented on a chip, the plurality of hardware threads including the slave hardware thread and a master hardware thread, the method comprising:

executing a software thread by the slave hardware thread;

receiving a status request for the slave hardware thread from the master hardware thread at an inbox associated with the slave hardware thread;

in response to receiving the status request at the inbox, determining a status associated with the slave hardware thread using status logic associated with the slave hardware thread; and

communicating a status response based on the status to the master hardware thread using the status logic;

wherein the status logic is implemented in hardware associated with the slave hardware thread and is configured to determine the status associated with the slave hardware thread and communicate the status response concurrently with execution of the software thread by the slave hardware thread and without interrupting execution of the software thread by the slave hardware thread.

2. The method of claim 1, wherein determining a status associated with the slave hardware thread comprises:

analyzing a status register associated with the slave hardware thread with the status logic to determine the status.

3. The method of claim 1, further comprising:

receiving a configuration message at the slave hardware thread from the master hardware thread; and

processing the configuration message at the slave hardware thread to configure the status logic of the slave hardware thread to automatically communicate a status response responsive to receiving a status request to the master hardware thread.

4. The method of claim 1, further comprising:

receiving the status response at the master hardware thread; and

storing status information for the slave hardware thread to memory based at least in part on the received status response.

5. The method of claim 4, further comprising:

prior to storing the status information for the slave hardware thread to memory, determining whether the status response is of a particular type by filtering the status response with a mask using thread status logic associated with the master hardware thread, wherein the status information is stored to memory responsive to determining that the status response is of the particular type.

6. The method of claim 1, further comprising:

receiving the status response at the master hardware thread; and

determining whether the status response is of a particular type.

7. The method of claim 6, further comprising:

in response to determining that the status response is of the particular type, communicating an interrupt message to the slave hardware thread.

8. The method of claim 6, wherein determining whether the status response is of a particular type comprises:

filtering the status response with thread status logic of the master hardware thread by with a mask.

9. The method of claim 1, further comprising:

communicating the status request from the master hardware thread;

monitoring the receipt of the status response at the master hardware thread to determine whether the status response was received within a predefined amount of time from communicating the status request.

10. The method of claim 9, further comprising:

communicating a notification from the master hardware thread responsive to not receiving the status response within the predefined amount of time.

11. The method of claim 1, wherein the plurality of hardware threads are connected to a network of the NOC processing system with a direct inter-thread communication interface.