Fault-tolerant dot product engine

• US 10,545,821 B2
• Filed: 07/31/2017
• Issued: 01/28/2020
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Roth, Ron M., Henze, Richard H.
• Primary Examiner(s): Chaudry, Mujtaba M
• Application Number:
  US15/664,874
• Publication Number:
  US 20190034268A1
• Time in Patent Office: 911 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence

Abstract

Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m<n of the n column lines in the crossbar array are programmed with matrix values used to detect errors in the output signal.

Claims

1. A fault-tolerant dot product engine, comprising:

a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×

n memory locations, each memory location comprising a programmable memristive element and defining a matrix value;

a number l of digital-to-analog converters coupled to the row lines of the crossbar array to receive an input signal; and

a number n of analog-to-digital converters coupled to the column lines of the crossbar array to generate an output signal that is a dot product of the input signal and the matrix values in the crossbar array,

wherein a number m<

n of the n column lines in the crossbar array are programmed with matrix values used to detect and correct errors in the output signal.

2. The fault-tolerant dot product engine of claim 1, wherein a first number k of values of the output signal represent a target dot product value and a number m of values of the output signal represent redundancy symbols, wherein k=n−

m.

3. The fault-tolerant dot product engine of claim 1, further comprising an encoder circuit to encode the matrix values in the m column lines in the crossbar array based on matrix values in a first set of k column lines in the crossbar array, wherein k=n−

m.

4. The fault-tolerant dot product engine of claim 2, further comprising a decoder circuit to detect and correct errors in the output signal.

5. The fault-tolerant dot product engine of claim 1, wherein the matrix values in the m column lines of the crossbar array are computed from the matrix values in a first number k of column lines of the crossbar array, wherein k=n−

m.

6. The fault-tolerant dot product engine of claim 3, wherein the encoder circuit generates the matrix values according to a desired number of errors to be detected using a Manhattan distance metric.

7. The fault-tolerant dot product engine of claim 3, wherein the encoder circuit generates the matrix values according to a desired number of errors to be detected using a Hamming distance metric.