Semiconductor package via stack checking

• US 10,546,096 B2
• Filed: 09/29/2017
• Issued: 01/28/2020
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Call, Anson J., Walling, Paul R.
• Primary Examiner(s): Nguyen, Nha T
• Application Number:
  US15/719,693
• Publication Number:
  US 20190102504A1
• Time in Patent Office: 851 Days
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.

Claims

1. A computer-implemented method for checking semiconductor package via proximity rules, the method comprising:

receiving, by a processor, the via proximity rules and a semiconductor package design comprising one or more package layers and a plurality of vias;

mapping each via to a cell in a three-dimensional array, the mapping based on a three-dimensional coordinate of each via in the semiconductor package design, wherein each cell in the three-dimensional array comprises a 32-digit binary number and each digit in the 32-digit binary number corresponds to a unique via;

identifying, for each via in the three-dimensional array, a via stack comprising the via;

determining whether each identified via stack satisfies the via proximity rules; and

displaying on a user interface a list of via stacks that do not satisfy the via proximity rules.

2. The method of claim 1, wherein a first identified via stack comprises a first height and a second identified via stack comprises a second height, the first and second heights dissimilar.

3. The method of claim 2, wherein the first identified via stack comprises a 2-high via stack and the second identified via stack comprises a 3-high via stack.

4. The method of claim 1, further comprising assigning a unique via definition to each via in the semiconductor package.

5. The method of claim 4, wherein each unique via definition comprises an identifier for each layer that is electrically coupled by the via and a diameter of the via at each layer.

6. The method of claim 1, wherein a position of each cell in the three-dimensional array comprises compressed x, y, and z coordinates of the semiconductor package design.

7. The method of claim 6, wherein the z coordinate identifies a package layer of the semiconductor package design and the x and y coordinates identify a relative location on the package layer.

8. The method of claim 1, wherein identifying a via stack for a via comprises identifying all other vias in the semiconductor package design that are exactly coincident to the via.

9. The method of claim 8, wherein identifying a via stack for a via further comprises identifying all other vias in the semiconductor package design that satisfy a stagger distance from the via.

10. The method of claim 9, wherein the stagger distance defines a maximum allowed centerline-to-centerline distance from the via.

11. A system for checking semiconductor package via proximity rules, the system having a processor coupled to a memory, the processor configured to:

receive the via proximity rules and a semiconductor package design comprising one or more package layers and a plurality of vias;

map each via to a cell in a three-dimensional array, the mapping based on a three-dimensional coordinate of each via in the semiconductor package design, wherein each cell in the three-dimensional array comprises a 32-digit binary number and each digit in the 32-digit binary number corresponds to a unique via;

identify, for each via in the three-dimensional array, a via stack comprising the via;

determine whether each identified via stack satisfies the via proximity rules; and

display on a user interface a list of via stacks that do not satisfy the via proximity rules.

12. The system of claim 11, further comprising assigning a unique via definition to each via in the semiconductor package.

13. The system of claim 12, wherein each unique via definition comprises an identifier for each layer that is electrically coupled by the via and a diameter of the via at each layer.

14. The system of claim 11, wherein identifying a via stack for a via comprises identifying all other vias in the semiconductor package design that are exactly coincident to the via.

15. The system of claim 14, wherein identifying a via stack for a via further comprises identifying all other vias in the semiconductor package design that satisfy a stagger distance from the via.

16. A computer program product for checking semiconductor package via proximity rules, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform:

receiving the via proximity rules and a semiconductor package design comprising one or more package layers and a plurality of vias;

mapping each via to a cell in a three-dimensional array, the mapping based on a three-dimensional coordinate of each via in the semiconductor package design, wherein each cell in the three-dimensional array comprises a 32-digit binary number and each digit in the 32-digit binary number corresponds to a unique via;

identifying, for each via in the three-dimensional array, a via stack comprising the via;

determining whether each identified via stack satisfies the via proximity rules; and

displaying on a user interface a list of via stacks that do not satisfy the via proximity rules.

17. The computer program product of claim 16, wherein a position of each cell in the three-dimensional array comprises compressed x, y, and z coordinates of the semiconductor package design.

18. The computer program product of claim 17, wherein the z coordinate identifies a package layer of the semiconductor package design and the x and y coordinates identify a relative location on the package layer.

19. The computer program product of claim 16, wherein a first identified via stack comprises a first height and a second identified via stack comprises a second height, the first and second heights dissimilar.