Multi-port random access memory

• US 10,546,624 B2
• Filed: 12/29/2017
• Issued: 01/28/2020
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: El-Baraji, Mourad, Berger, Neal, Crudele, Lester, Louie, Benjamin
• Primary Examiner(s): Norman, James G
• Application Number:
  US15/858,398
• Publication Number:
  US 20190206468A1
• Time in Patent Office: 760 Days
• Field of Search: None
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).

Claims

1. A memory device, comprising:

a write port;

a read port;

a plurality of source lines, a plurality of bit lines, and a plurality of word lines, wherein the word lines are orthogonal to the bit lines; and

an array of memory cells coupled to the write port, the read port, the source lines, the bit lines, and the word lines, wherein the memory cells are arrayed in a plurality of columns that are parallel to the bit lines and in a plurality of rows that are orthogonal to the bit lines, and wherein each memory cell of the memory cells comprises a respective magnetoresistive random access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ) that stores a respective binary bit value;

wherein a first memory cell of the memory cells comprises a first transistor having a first gate coupled to a first word line of the plurality of word lines and a first source coupled to a first source line of the plurality of source lines, a second transistor having a second gate coupled to a second word line of the plurality of word lines and a second source coupled to a second source line of the plurality of source lines, and a first storage element for storing a first binary bit value, and wherein a second memory cell of the memory cells comprises a third transistor having a third gate coupled to a third word line of the plurality of word lines and a third source coupled to a third source line of the plurality of source lines, a fourth transistor having a fourth gate coupled to a fourth word line of the plurality of word lines and a fourth source coupled to a fourth source line of the plurality of source lines, and a second storage element for storing a second binary bit value, and

wherein a write by the write port to the first memory cell comprises activating the first transistor with a first voltage provided over the first word line to the first gate while the second transistor is inactive and while a current is supplied to a first bit line then to the first storage element and the first transistor to the first source line; and

wherein a read by the read port of the second memory cell comprises activating the fourth transistor with a second voltage provided over the fourth word line to the fourth gate while the third transistor is inactive and while a current is supplied to a second bit line then to the second storage element and the fourth transistor to the fourth source line, wherein the first and second bit lines are different.

2. The memory device of claim 1, wherein the first voltage is greater than the second voltage.

3. The memory device of claim 1, further comprising a second write port, wherein the first memory cell further comprises a fifth transistor having a fifth gate coupled to a fifth word line of the plurality of word lines and a fifth source coupled to a fifth source line of the plurality of source lines;

and

wherein a write by the second write port to the first memory cell comprises activating the fifth transistor with a third voltage provided over the fifth word line to the fifth gate while the first and second transistors are inactive and while a current is supplied to the first bit line then to the first storage element and the fifth transistor to the fifth source line.

4. The memory device of claim 1, further comprising a second read port, wherein the second memory cell further comprises a fifth transistor having a fifth gate coupled to a fifth word line of the plurality of word lines and a fifth source coupled to a fifth source line of the plurality of source lines;

and

wherein a read by the second read port of the second memory cell comprises activating the fifth transistor with a third voltage provided over the fifth word line to the fifth gate while the third and fourth transistors are inactive and while a current is supplied to the second bit line then to the second storage element and the fifth transistor to the fifth source line.

5. The memory device of claim 1, wherein the write is followed by a verify of the first memory cell.

6. A memory device, comprising:

a write port and a read port; and

an array of memory cells coupled to the write port and to the read port, wherein each memory cell of the array is coupled to a respective bit line and comprises a respective storage element, respective write circuitry, and respective read circuitry;

wherein, for each said memory cell, the write circuitry comprises a first transistor having a first gate coupled to receive a first voltage from a first word line and also having a first source coupled to a first source line, and the read circuitry comprises a second transistor having a second gate coupled to receive a second voltage from a second word line and also having a second source coupled to a second source line, wherein the first transistor is active during a first write to the storage element but is inactive during a first read of the storage element, and wherein the second transistor is active during the first read but is inactive during the first write, wherein for the first write a current is supplied from the write port to the respective bit line to the storage element and to the first transistor to the first source line, and wherein for the first read a current is supplied from the read port to the respective bit line to the storage element and to the second transistor to the second source line.

7. The memory device of claim 6, wherein the array of memory cells comprises:

a first memory cell coupled to a first bit line; and

a second memory cell coupled to a second bit line different from the first bit line, wherein a write to the first memory cell and a read of the second memory cell are both executed during overlapping time periods.

8. The memory device of claim 7, wherein the write is followed by a verify of the first memory cell.

9. The memory device of claim 6, wherein the first voltage is greater than the second voltage.

10. The memory device of claim 6, further comprising a second write port, wherein the respective write circuitry of said each memory cell further comprises a third transistor having a third gate coupled to receive a third voltage from a third word line and also having a third source coupled to a third source line, wherein the third transistor is active during a second write but is inactive during the first write and during the first read, and wherein the first and second transistors are inactive during the second write, and wherein for the second write a current is supplied from the second write port to the respective bit line to the storage element and to the third transistor to the third source line.

11. The memory device of claim 6, further comprising a second read port, wherein the respective read circuitry of said each memory cell further comprises a third transistor having a third gate coupled to receive a third voltage from a third word line and also having a third source coupled to a third source line, wherein the third transistor is active during a second read but is inactive during the first write and during the first read, and wherein the first and second transistors are inactive during the second read, and wherein for the second read a current is supplied from the second read port to the respective bit line to the storage element and to the third transistor to the third source line.

12. The device of claim 6, wherein the storage element comprises a magnetoresistive random access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ) that stores a binary bit value.

13. In a memory device comprising a write port, a read port, and memory cells, a method comprising:

performing a write, by the write port, to a first memory cell of the memory cells in a column parallel to a first bit line; and

performing a read, by the read port, of a second memory cell of the memory cells in a column parallel to a second bit line, when the second bit line is different from the first bit line;

wherein the first memory cell comprises a first transistor having a first gate coupled to a first word line and a first source coupled to a first source line, a second transistor having a second gate coupled to a second word line and a second source coupled to a second source line, and a first storage element for storing a first binary bit value, and wherein the second memory cell comprises a third transistor having a third gate coupled to a third word line and a third source coupled to a third source line, a fourth transistor having a fourth gate coupled to a fourth word line and a fourth source coupled to a fourth source line, and a second storage element for storing a second binary bit value;

wherein the method further comprises;

for the write to the first memory cell, activating the first transistor with a first voltage provided over the first word line to the first gate while the second transistor is inactive and while supplying a current to the first bit line then to the first storage element and the first transistor to the first source line; and

for the read of the second memory cell, activating the fourth transistor with a second voltage provided over the fourth word line to the fourth gate while the third transistor is inactive and while supplying a current to the second bit line then to the second storage element and the fourth transistor to the fourth source line.

14. The method of claim 13, further comprising performing a verify of the first memory cell after the write to the first memory cell.

15. The method of claim 13, wherein the memory device further comprises a second write port, wherein the first memory cell further comprises a fifth transistor having a fifth gate coupled to a fifth word line and a fifth source coupled to a fifth source line, the method further comprising, for a write by the second write port to the first memory cell, activating the fifth transistor with a third voltage provided over the fifth word line to the fifth gate while the first and second transistors are inactive and while supplying a current to the first bit line then to the first storage element and the fifth transistor to the fifth source line.

16. The method of claim 13, wherein the memory device further comprises a second read port, wherein the second memory cell further comprises a fifth transistor having a fifth gate coupled to a fifth word line and a fifth source coupled to a fifth source line, the method further comprising, for a read, by the second read port, of the second memory cell, activating the fifth transistor with a third voltage provided over the fifth word line to the fifth gate while the third and fourth transistors are inactive and while supplying a current to the second bit line then to the second storage element and the fifth transistor to the fifth source line.

17. The method of claim 13, wherein each memory cell of the memory cells comprises a respective magnetoresistive random access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ) that stores a respective binary bit value.