Method of optimizing write voltage based on error buffer occupancy

• US 10,546,625 B2
• Filed: 08/30/2018
• Issued: 01/28/2020
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, Kim, Kuk-Hwan, Pyon, Taejin
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US16/118,137
• Publication Number:
  US 20190139590A1
• Time in Patent Office: 516 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

Claims

1. A method of storing data to a memory device, the method comprising:

utilizing write logic to perform writes to a memory space of a first set of write operations that address the memory space;

storing a second set of write operations into a cache memory, wherein the write operations of the second set are write operations of said first set that have not completed writing to said memory space;

removing, from said cache memory, write operations thereof that complete writing to said memory space;

monitoring an occupancy level of write operations within the cache memory;

determining if the occupancy level reaches a predetermined threshold; and

responsive to the determining, increasing a write voltage level associated with the memory space to a higher write voltage level.

2. A method of claim 1 further comprising responsive to the increasing the write voltage level, utilizing the write logic to perform write operations to the memory space using the higher write voltage level.

3. A method of claim 1 wherein the write logic comprises a pipeline architecture.

4. A method of claim 1 wherein each write operation stored in the cache memory is either awaiting write verification or comprises a data word that is to be re-written into the memory space.

5. A method of claim 1 wherein the cache memory is associated with the memory space.

6. A method of claim 1 wherein the memory space comprises a plurality of magnetic random access memory (MRAM) cells.

7. A method of claim 1 further comprising:

determining if the occupancy level falls below the predetermined threshold;

responsive to the determining if the occupancy level falls below the predetermined threshold, decreasing the higher write voltage level to a lower voltage level; and

responsive to the decreasing the higher write voltage level, utilizing the write logic to perform write operations to the memory space using the lower write voltage level.

8. A method of claim 1 further comprising:

responsive to the determining if the occupancy level reaches the predetermined threshold, determining that the write voltage level is at a voltage level high threshold;

responsive to the write voltage level being at the voltage level high threshold, increasing a pulse width for write cycles of the memory space; and

utilizing the write logic to perform write operations to the memory space using an increased pulse width.

9. A method as described in claim 1 wherein write operations of said first set comprise respective data words addressed to said memory space.

10. A method as described in claim 1, wherein the increasing the write voltage of the memory bank comprises:

transmitting a signal to a digital-to-analog converter (DAC), wherein the DAC controls write drivers on the memory space to drive source and bit lines associated with memory cells of the memory space at the higher write voltage during writing.

11. A method of storing data to a memory device, the method comprising:

utilizing write logic to perform writes to a memory space of a first set of write operations that address the memory space;

storing a second set of write operations into a cache memory, wherein the write operations of the second set are write operations of said first set that have not completed writing to said memory space;

removing, from said cache memory, write operations thereof that complete writing to said memory space;

monitoring an occupancy level of write operations within the cache memory;

determining if the occupancy level is larger than a predetermined threshold; and

responsive to the determining, increasing a length of a pulse width for write cycles of the memory space.

12. A method of claim 11 further comprising responsive to the increasing the pulse width, utilizing the write logic to perform write operations to the memory space using an increased pulse width.

13. A method of claim 11 wherein the write logic comprises a pipeline architecture.

14. A method of claim 11 wherein each write operation stored in the cache memory is either awaiting write verification or comprises a data word that is to be re-written into the memory space.

15. A method of claim 11 wherein the cache memory is associated with the memory space.

16. A method of claim 11 wherein the memory space comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

17. A method of claim 11 further comprising:

determining if the occupancy level falls below the predetermined threshold;

responsive to the determining if the occupancy level falls below the predetermined threshold, decreasing the length of pulse width for the write cycles; and

responsive to the decreasing the pulse width, utilizing the write logic to perform write operations to the memory space using a shorter pulse width.

18. A method as described in claim 11 wherein write operations of said first set comprise respective data words addressed to said memory space.

19. A method as described in claim 11, wherein the increasing the write voltage of the memory bank comprises:

transmitting a signal to a write pulse-width control module, wherein the write pulse width control module controls write drivers on said memory space to drive source and bit lines associated with memory cells of said memory space to control the pulse width during write cycles.

20. The method of claim 11, wherein the determining comprises:

calculating, based on a plurality of status bits from the cache memory, if the occupancy level of the cache memory is larger than the predetermined threshold.

21. A memory device for storing data, the memory device comprising:

a memory bank comprising a plurality of addressable memory cells;

a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank;

a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank; and

a logic module operable to;

monitor an occupancy level of the error buffer;

determine if the occupancy level of the error buffer exceeds a predetermined threshold; and

responsive to a determination that the occupancy level of the error buffer exceeds the predetermined threshold, increase a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.