System and method for substrate wafer back side and edge cross section seals

• US 10,546,750 B2
• Filed: 01/05/2016
• Issued: 01/28/2020
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Vishay-Siliconix
• Original Assignee: Vishay-Siliconix
• Inventors: Lu, Hamilton, Chau, The-Tu, Terrill, Kyle, Pattanayak, Deva N., Shi, Sharon, Chen, Kuo-In, Xu, Robert
• Primary Examiner(s): Wright, Tucker J
• Assistant Examiner(s): Stowe, Scott
• Application Number:
  US14/988,639
• Publication Number:
  US 20160225622A1
• Time in Patent Office: 1,484 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/2205 from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Claims

1. A method of growing epitaxial silicon on a silicon wafer, said method comprising:

depositing a layer of silicon oxide on all entire surfaces and edges of said silicon wafer;

removing said silicon oxide from a front surface of said silicon wafer;

depositing a layer of poly silicon only on a back surface of said silicon wafer, over said silicon oxide;

growing a layer of epitaxial silicon on said front surface of said silicon wafer;

depositing another layer of silicon oxide on all exposed surfaces and edges of said layer of epitaxial silicon and said silicon wafer;

removing said another layer of silicon oxide from a front surface of said layer of epitaxial silicon;

depositing another layer of poly silicon on the back surface of said silicon wafer, over said another layer of silicon oxide; and

growing another layer of epitaxial silicon on said layer of epitaxial silicon.

2. The method of claim 1 wherein said depositing a layer of silicon oxide is configured to reduce auto doping during said growing.

3. The method of claim 1 further comprising doping a region of said layer of epitaxial silicon prior to said growing another layer of epitaxial silicon.

4. The method of claim 1 wherein said another layer of epitaxial silicon comprises a gap characterized by an absence of epitaxial silicon.

5. The method of claim 1 wherein no epitaxial silicon is in contact with silicon of a back side of said wafer.