Methods of forming V0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness

• US 10,546,854 B2
• Filed: 06/05/2015
• Issued: 01/28/2020
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Zhang, Xunyuan
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Nguyen, Lawrence-Linh T
• Application Number:
  US14/732,038
• Publication Number:
  US 20160358908A1
• Time in Patent Office: 1,698 Days
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.

Claims

1. A method of forming a V0 via on an integrated circuit product comprised of two spaced-apart transistor gate structures, each of said gate structures having a gate cap layer, the method comprising:

forming a source/drain contact structure between said two spaced-apart transistor gate structures, wherein an uppermost surface of said source/drain contact structure is substantially coplanar with an uppermost surface of each of said gate cap layers;

performing a deposition process to form a non-uniform thickness layer of insulating material directly on said uppermost surface of said gate cap layers and directly on said uppermost surface of said source/drain contact structure, wherein portions of said non-uniform thickness layer of insulating material positioned on said uppermost surface of said gate cap layers have a first thickness and a portion of said non-uniform thickness layer of insulating material positioned on said uppermost surface of said source/drain contact structure has a second thickness that is substantially less than said first thickness;

forming a first layer of insulating material above said non-uniform thickness layer of insulating material;

performing at least one etching process to form an opening in said non-uniform thickness layer of insulating material so as to expose at least a portion of said source/drain contact structure; and

forming said V0 via such that it is conductively coupled to said exposed portion of said source/drain contact structure, said V0 via being at least partially positioned in said opening in said non-uniform thickness layer of insulating material.

2. The method of claim 1, wherein forming said source/drain contact structure comprises:

forming a line-type trench silicide contact that is conductively coupled to a source/drain region positioned between said two gate structures; and

forming a line-type CA contact structure comprised of tungsten on said line-type trench silicide contact, wherein said uppermost surface of said contact structure is an uppermost surface of said line-type CA contact structure.

3. The method of claim 1, wherein forming said source/drain contact structure comprises forming said source/drain contact structure such that an upper portion of said source/drain contact structure is comprised of tungsten.

4. The method of claim 1, wherein performing said deposition process to form said non-uniform thickness layer of insulating material comprises performing said deposition process such that said first thickness is at least 10-30 nm greater than said second thickness.

5. The method of claim 1, wherein performing said deposition process to form said non-uniform thickness layer of insulating material comprises performing said deposition process such that said first thickness falls within a range of about 15-55 nm, while said second thickness falls within a range of about 5-25 nm.

6. The method of claim 1, wherein performing said deposition process to form said non-uniform thickness layer of insulating material comprises performing a TELOS deposition process to form said non-uniform thickness layer of insulating material.

7. The method of claim 1, wherein said two gate structures are each a replacement gate structure comprised of a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

8. The method of claim 1, wherein, after forming said first layer of insulating material and prior to performing said at least one etching process, the method further comprises forming an opening in said first layer of insulating material so as to expose a portion of said non-uniform thickness layer of insulating material.

9. The method of claim 1, wherein forming said V0 via comprises forming said V0 via such that a portion of said V0 via is positioned vertically above said gate cap layer of at least one of said two gate structures and above a portion of said patterned non-uniform thickness layer of insulating material.

15. The method of claim 1, wherein a bottom surface of said non-uniform thickness layer of insulating material is substantially planar.

10. A method of forming a V0 via on an integrated circuit product comprised of two spaced-apart transistor gate structures, each of said gate structures having a gate cap layer, the method comprising:

forming a line-type trench silicide contact that is conductively coupled to a source/drain region positioned between said two gate structures;

forming a line-type CA contact structure comprised of tungsten on said line-type trench silicide contact, wherein an upper surface of said line-type CA contact structure is substantially coplanar with an upper surface of each of said gate cap layers;

performing a deposition process to form a non-uniform thickness layer of insulating material on said upper surface of said gate cap layers and on said upper surface of said line-type CA contact structure, wherein portions of said non-uniform thickness layer of insulating material positioned on said upper surface of said gate cap layers have a first thickness and a portion of said non-uniform thickness layer of insulating material positioned on said upper surface of said line-type CA contact structure has a second thickness, said first thickness being at least 10-30 nm greater than said second thickness;

forming a first layer of insulating material above said non-uniform thickness layer of insulating material;

performing at least one etching process to form an opening in said non-uniform thickness layer of insulating material so as to expose at least a portion of said line-type CA contact structure; and

forming said V0 via such that it is conductively coupled to said exposed portion of said line-type CA contact structure, said V0 via being at least partially positioned in said opening in said non-uniform thickness layer of insulating material.

11. The method of claim 10, wherein performing said deposition process to form said non-uniform thickness layer of insulating material comprises performing said deposition process such that said first thickness falls within a range of about 15-55 nm, while said second thickness falls within a range of about 5-25 nm.

12. The method of claim 10, wherein performing said deposition process to form said non-uniform thickness layer of insulating material comprises performing a TELOS deposition process to form said non-uniform thickness layer of insulating material.

13. The method of claim 10, wherein, after forming said first layer of insulating material and prior to performing said at least one etching process, the method further comprises forming an opening in said first layer of insulating material so as to expose a portion of said non-uniform thickness layer of insulating material.

14. The method of claim 10, wherein forming said V0 via comprises forming said V0 via such that a portion of said V0 via is positioned vertically above said gate cap layer of at least one of said two gate structures and above a portion of said patterned non-uniform thickness layer of insulating material.

16. The method of claim 10, wherein a bottom surface of said non-uniform thickness layer of insulating material is substantially planar.

17. A method of forming a V0 via on an integrated circuit product comprised of two spaced-apart transistor gate structures, each of said gate structures having a gate cap layer, the method comprising:

forming a source/drain contact structure between said two spaced-apart transistor gate structures, wherein an uppermost surface of said source/drain contact structure is substantially planar with an uppermost surface of each of said gate cap layers;

performing a TELOS deposition process to form a non-uniform thickness layer of material on said uppermost surface of said gate cap layers and on said uppermost surface of said source/drain contact structure, wherein portions of said non-uniform thickness layer of material positioned on said gate cap layers have a first thickness and a portion of said non-uniform thickness layer of material positioned on said source/drain contact structure has a second thickness that is substantially less than said first thickness;

forming a first layer of insulating material above said non-uniform thickness layer of material;

performing at least one etching process to form an opening in said non-uniform thickness layer of material so as to expose at least a portion of said source/drain contact structure; and

forming said V0 via such that it is conductively coupled to said exposed portion of said source/drain contact structure, said V0 via being at least partially positioned in said opening in said non-uniform thickness layer of material.

18. The method of claim 17, wherein forming said source/drain contact structure comprises forming said source/drain contact structure such that an upper portion of said source/drain contact structure is comprised of tungsten.

19. The method of claim 17, wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing said deposition process such that said first thickness is at least 10-30 nm greater than said second thickness.

20. The method of claim 17, wherein performing said deposition process to form said non-uniform thickness layer of material comprises performing said deposition process such that said first thickness falls within a range of about 15-55 nm, while said second thickness falls within a range of about 5-25 nm.

21. The method of claim 17, wherein said two gate structures are each a replacement gate structure comprised of a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

22. The method of claim 17, wherein, after forming said first layer of insulating material and prior to performing said at least one etching process, the method further comprises forming an opening in said first layer of insulating material so as to expose a portion of said non-uniform thickness layer of material.

23. The method of claim 17, wherein forming said V0 via comprises forming said V0 via such that a portion of said V0 via is positioned vertically above said gate cap layer of at least one of said two gate structures and above a portion of said patterned non-uniform thickness layer of material.