NAND string utilizing floating body memory cell
First Claim
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1. A NAND string configuration comprising:
- a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region; and
a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;
wherein each said at least one of said plurality of semiconductor memory cells has only one gate; and
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.
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Abstract
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
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14 Claims
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1. A NAND string configuration comprising:
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a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells; a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; and a select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell; wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region; and
a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; wherein each said at least one of said plurality of semiconductor memory cells has only one gate; and wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory array comprising:
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a plurality of NAND string configurations, each said NAND string configuration comprising; a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells; a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and a select gate source device connected an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device; wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; wherein each said at least one of said plurality of semiconductor memory cells has only one gate; wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals; and wherein said semiconductor memory array comprises at least one of;
at least two of said select gate drain devices connected to a common bit line;
or at least two of said select gate source devices connected to a common source line. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification