Thin film transistor array substrate and display panel

• US 10,546,881 B2
• Filed: 08/27/2018
• Issued: 01/28/2020
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Inventors: Fan, Yingchun, Zhang, Xiaoxing
• Primary Examiner(s): Menz, Laura M
• Application Number:
  US16/086,017
• Publication Number:
  US 20190326325A1
• Time in Patent Office: 519 Days
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

A thin film transistor array substrate and a display panel are provided. The thin film transistor array substrate includes a substrate, a thin film transistor, a scan line, a data line and a pixel electrode. The thin film transistor includes a semiconductor member, a gate electrode, a source electrode and a drain electrode. The source electrode and the drain electrode include a first extension portion and a second extension portion, respectively. The first extension portion and the second extension portion are configured to block light that is emitted toward an electron migration channel of the thin film transistor. Thus, external light emitting toward the electron migration channel can be prevented.

Claims

1. A thin film transistor array substrate, comprising a substrate, a thin film transistor, a scan line, a data line and a pixel electrode, wherein the thin film transistor comprises a semiconductor member, a gate electrode, a source electrode, and a drain electrode;

the thin film transistor further comprising;

a light shielding member disposed on the substrate;

a buffer layer disposed on the substrate and the light shielding member;

a first insulating layer disposed between the gate electrode and the semiconductor member; and

a second insulating layer covering at least a portion of the buffer layer, the semiconductor member, the first insulating layer, and the gate electrode;

wherein at least a portion of the source electrode and at least a portion of the drain electrode are disposed on the second insulating layer, the source electrode is connected to a first contact portion of the semiconductor member through penetrating a first through hole of the second insulating layer, and the drain electrode is connected to a second contact portion of the semiconductor member through penetrating a second through hole of the second insulating layer;

wherein a portion of the source electrode disposed on the second insulating layer comprises a first extension portion, a portion of the drain electrode disposed on the second insulating layer comprises a second extension portion, and both of the first extension portion and the second extension portion are configured to block external light that is emitted from an outside of the thin film transistor array substrate to an electron migration channel of the thin film transistor;

wherein the first extension portion extends from a body of the source electrode toward the drain electrode;

wherein a first projection of the first extension portion projected on a plane where the thin film transistor array substrate is located overlaps a second projection projected on a plane, where the thin film transistor array substrate is located, of a first gap between the body of the source electrode and the gate electrode;

wherein the second extension portion extends from a body of the drain electrode toward the source electrode; and

wherein a third projection of the second extension portion projected on a plane where the thin film transistor array substrate is located overlaps a fourth projection projected on a plane, where the thin film transistor array substrate is located, of a second gap between the body of the drain electrode and the gate electrode;

wherein when both of the source electrode and the drain electrode are made of a light-permeable metal, a first light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion, and a second light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion.

2. The thin film transistor array substrate according to claim 1, wherein both of the first extension portion and the second extension portion are made of opaque metal.

3. A thin film transistor array substrate, the thin film transistor array substrate comprising a substrate, a thin film transistor, a scan line, a data line and a pixel electrode, wherein the thin film transistor comprises a semiconductor member, a gate electrode, a source electrode and a drain electrode;

the thin film transistor further comprising;

a light shielding member disposed on the substrate;

a buffer layer disposed on the substrate and the light shielding member;

a first insulating layer disposed between the gate electrode and the semiconductor member; and

a second insulating layer covering at least a portion of the buffer layer, the semiconductor member, the first insulating layer, and the gate electrode;

wherein at least a portion of the source electrode and at least a portion of the drain electrode are disposed on the second insulating layer, the source electrode is connected to a first contact portion of the semiconductor member through penetrating a first through hole of the second insulating layer, and the drain electrode is connected to a second contact portion of the semiconductor member through penetrating a second through hole of the second insulating layer; and

wherein a portion of the source electrode disposed on the second insulating layer comprises a first extension portion, a portion of the drain electrode disposed on the second insulating layer comprises a second extension portion, and both of the first extension portion and the second extension portion are configured to block external light that is emitted from an outside of the thin film transistor array substrate to an electron migration channel of the thin film transistor;

wherein when both of the source electrode and the drain electrode are made of a light-permeable metal, a first light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion, and a second light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion.

4. The thin film transistor array substrate according to claim 3, wherein the first extension portion extends from a body of the source electrode toward the drain electrode.

5. The thin film transistor array substrate according to claim 3, wherein a first projection of the first extension portion projected on a plane where the thin film transistor array substrate is located overlaps a second projection projected on a plane, where the thin film transistor array substrate is located, of a first gap between the body of the source electrode and the gate electrode.

6. The thin film transistor array substrate according to claim 3, wherein the second extension portion extends from a body of the drain electrode toward the source electrode.

7. The thin film transistor array substrate according to claim 3, wherein a third projection of the second extension portion projected on a plane where the thin film transistor array substrate is located overlaps a fourth projection projected on a plane, where the thin film transistor array substrate is located, of a second gap between the body of the drain electrode and the gate electrode.

8. The thin film transistor array substrate according to claim 3, wherein both of the first extension portion and the second extension portion are made of opaque metal.

9. The thin film transistor array substrate according to claim 3, wherein the first light shielding sheet is disposed between the first extension portion and the second insulating layer, or the first light shielding sheet is disposed on a surface of the first extension portion facing away from the second insulating layer;

and

the second light shielding sheet is disposed between the second extension portion and the second insulating layer, or the second light shielding sheet is disposed on a surface of the second extension portion facing away from the second insulating layer.

10. The thin film transistor array substrate according to claim 3, wherein both of the first light shielding sheet and the second light shielding sheet are configured to block external light that is emitted from the outside of the thin film transistor array substrate to the electron migration channel of the thin film transistor.

11. A display panel, comprising a thin film transistor array substrate and a display device, the display device laminated and combined with the thin film transistor array substrate, the thin film transistor array substrate comprising a substrate, a thin film transistor, a scan line, a data line and a pixel electrode, wherein the thin film transistor comprises a semiconductor member, a gate electrode, a source electrode and a drain electrode;

the thin film transistor further comprising;

a light shielding member disposed on the substrate;

a buffer layer disposed on the substrate and the light shielding member;

a first insulating layer disposed between the gate electrode and the semiconductor member; and

a second insulating layer covering at least a portion of the buffer layer, the semiconductor member, the first insulating layer, and the gate electrode;

wherein at least a portion of the source electrode and at least a portion of the drain electrode are disposed on the second insulating layer, the source electrode is connected to a first contact portion of the semiconductor member through penetrating a first through hole of the second insulating layer, and the drain electrode is connected to a second contact portion of the semiconductor member through penetrating a second through hole of the second insulating layer; and

wherein a portion of the source electrode disposed on the second insulating layer comprises a first extension portion, a portion of the drain electrode disposed on the second insulating layer comprises a second extension portion, and both of the first extension portion and the second extension portion are configured to block external light that is emitted from an outside of the thin film transistor array substrate to an electron migration channel of the thin film transistor;

wherein when both of the source electrode and the drain electrode are made of a light-permeable metal, a first light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion, and a second light shielding sheet made of an opaque metal is disposed at a position on the second insulating layer and corresponding to the first extension portion.

12. The display panel according to claim 11, wherein the first extension portion extends from a body of the source electrode toward the drain electrode.

13. The display panel according to claim 11, wherein a first projection of the first extension portion projected on a plane where the thin film transistor array substrate is located overlaps a second projection projected on a plane, where the thin film transistor array substrate is located, of a first gap between the body of the source electrode and the gate electrode.

14. The display panel according to claim 11, wherein the second extension portion extends from a body of the drain electrode toward the source electrode.

15. The display panel according to claim 11, wherein a third projection of the second extension portion projected on a plane where the thin film transistor array substrate is located overlaps a fourth projection projected on a plane, where the thin film transistor array substrate is located, of a second gap between the body of the drain electrode and the gate electrode.

16. The display panel according to claim 11, wherein both of the first extension portion and the second extension portion are made of opaque metal.

17. The display panel according to claim 11, wherein the first light shielding sheet is disposed between the first extension portion and the second insulating layer, or the first light shielding sheet is disposed on a surface of the first extension portion facing away from the second insulating layer;

and

the second light shielding sheet is disposed between the second extension portion and the second insulating layer, or the second light shielding sheet is disposed on a surface of the second extension portion facing away from the second insulating layer.

18. The display panel according to claim 11, wherein both of the first light shielding sheet and the second light shielding sheet are configured to block external light that is emitted from the outside of the thin film transistor array substrate to the electron migration channel of the thin film transistor.