Semiconductor device with voltage resistant structure

• US 10,546,921 B2
• Filed: 01/17/2018
• Issued: 01/28/2020
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/873,686
• Publication Number:
  US 20180145129A1
• Time in Patent Office: 741 Days
• Field of Search: 257 77, 257328, 257330-334
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Claims

1. A semiconductor device comprising:

a cell region in which a circuit element is formed;

a gate trench formed in the cell region;

a source region formed around the gate trench;

a first conductivity type outer peripheral portion formed on a periphery of the cell region;

a concave portion formed on a surface of the outer peripheral portion;

a second conductivity type surface doping region formed on a periphery of the concave portion; and

a surface insulating film disposed in a manner extending across the cell region and the outer peripheral portion, and having a first thickness in the cell region thinner than a second thickness in the outer peripheral portion.

2. The semiconductor device according to claim 1, wherein

the gate trench is formed in a lattice pattern such that the gate trench defines the source region in each area surrounded by the lattice pattern,

the semiconductor device includes a source electrode connecting between a plurality of the source regions.

3. The semiconductor device according to claim 1, wherein

a plurality of the concave portions and the surface doping regions are formed in a direction toward a periphery of the semiconductor device.

4. The semiconductor device according to claim 1, wherein a plurality of the concave portions are arranged at regular intervals.

5. The semiconductor device according to claim 3, wherein

the plurality of concave portions include a first shape having a first width and a second shape having a second width.

6. The semiconductor device according to claim 1, further comprising a conductive member embedded in the concave portion.

7. The semiconductor device according to claim 2, wherein

a plurality of the concave portions and the surface doping regions are formed in a direction toward a periphery of the semiconductor device.

8. The semiconductor device according to claim 3, wherein the plurality of concave portions are arranged at regular intervals.

9. The semiconductor device according to claim 4, wherein

the plurality of concave portions include a first shape having a first width and a second shape having a second width.

10. The semiconductor device according to claim 1, further comprising a conductive member embedded in the concave portion through an insulating film.

11. The semiconductor device according to claim 1, wherein the semiconductor device includes a semiconductor layer made of SiC, GaN, or diamond.