Semiconductor device

• US 10,546,954 B2
• Filed: 05/21/2019
• Issued: 01/28/2020
• Est. Priority Date: 09/07/2009
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Mitani, Shuhei, Nakano, Yuki, Watanabe, Heiji, Shimura, Takayoshi, Hosoi, Takuji, Kirino, Takashi
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US16/418,360
• Publication Number:
  US 20190273158A1
• Time in Patent Office: 252 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0445 the devices having semiconductor bodies comprising crystalline silicon carbide multistep processes for the manufacture of said devices H01L29/66053
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Claims

1. A semiconductor device comprising:

a silicon carbide layer;

a gate trench formed at a surface of the silicon carbide layer;

a gate insulating film formed over the gate trench; and

a gate electrode formed over the gate insulating film,

wherein the silicon carbide layer includes a drain region, a well region formed over the drain region, and a source region formed over the well region,

wherein the gate trench is formed through the well region and to the surface of the silicon carbide layer so that a part of the gate insulating film is exposed from the gate trench at the surface of the silicon carbide layer, and

wherein, in a cross-sectional view, a width of the gate insulating film from one side of the gate trench to an opposite side of the gate trench is greater at a wider trench portion of the silicon carbide layer in which the source region is formed than at a base of the gate trench, and the wider trench portion includes a curved portion where the gate trench becomes wide.

2. The semiconductor device according to claim 1, wherein

a thickness of the gate insulating film is not less than 1 nm.

3. The semiconductor device according to claim 2, wherein

the silicon carbide layer is of a first conductivity type,

the semiconductor device further comprises:

the well region formed of a second conductivity type at a surface layer portion of the silicon carbide layer between the source region and the drain region; and

the source region formed of a first conductivity type at a surface layer portion of the well region,

wherein the gate electrode is opposed to a channel region of the well region where a channel is formed along the surface of the gate insulating film.

4. The semiconductor device according to claim 3, wherein an impurity concentration in a first region of a prescribed width adjacent to the channel region is lower than an impurity concentration in a second region other than the first region in the source region.

5. The semiconductor device according to claim 3, wherein

the source region and the channel region are adjacently formed in a direction along an inner surface of the gate trench, and

the gate insulating film is formed on the surface of the silicon carbide layer within the gate trench.

6. The semiconductor device according to claim 3, wherein

the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the silicon carbide layer, and

the gate trench extends down from the upper surface of the source region and passes through the source region to the well region, and

the gate insulating film is formed on the inner surface of the trench.

7. The semiconductor device according to claim 1, wherein a width of the source region in a vertical direction is smaller than a width of the well region in the vertical direction.

8. The semiconductor device according to claim 1, wherein the drain region contacts both a sidewall and a bottom wall of the gate trench.

9. The semiconductor device according to claim 1, further comprising a contact region of a second conductivity type at the surface of the silicon carbide layer.

10. The semiconductor device according to claim 9, wherein the contact region reaches to the well region in a vertical direction.

11. The semiconductor device according to claim 1, wherein a width of the source region in a vertical direction is about 0.2 μ

m.

12. The semiconductor device of claim 1, wherein the gate insulating film is formed along the inner surface of the gate trench and the gate electrode is formed in the gate trench and spaced apart from the inner surface of the gate trench by the gate insulating film.

13. The semiconductor device of claim 12, wherein the curved portion of the wider trench portion is formed on the surface of the silicon carbide layer and spaced from the upper surface of the silicon carbide layer by a surface extending from the curved surface to the upper surface of the silicon carbide layer, wherein the surface extending to the upper surface of the silicon carbide layer opposes the surface of the gate electrode and is parallel therewith.