Nanosheet FET including all-around source/drain contact

• US 10,546,957 B2
• Filed: 01/11/2018
• Issued: 01/28/2020
• Est. Priority Date: 01/11/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Xu, Peng, Yeung, Chun Wing, Zhang, Chen
• Primary Examiner(s): Williams, Alexander O
• Application Number:
  US15/868,742
• Publication Number:
  US 20190214502A1
• Time in Patent Office: 747 Days
• Field of Search: 257347
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming at least one semiconductor nanosheet in a channel region of a semiconductor wafer;

covering a first source/drain epitaxy structure formed on first sacrificial region with a first interlayer dielectric (ILD), and covering the second source/drain epitaxy structure formed on a second sacrificial layer with a second ILD; and

replacing the first and second sacrificial regions and a portion of the first and second ILDs with an electrically conductive material to form an all-around source/drain contact that encapsulates the first and second source/drain epitaxy structures.

2. The method of claim 1, further comprising growing, from the first sacrificial region, the first source/drain epitaxy structure to contact a first end of the at least one nanosheet, and growing, from the second sacrificial region, the second source/drain epitaxy structure to contact an opposing second end of the at least one nanosheet

wherein the first and second source/drain epitaxy structures each have a pair of opposing epitaxy sidewalls extending between an upper epitaxy surface and a lower epitaxy surface, and wherein the electrically conductive material contacts the upper epitaxy surface, the lower epitaxy surface and one of the epitaxy sidewalls.

3. The method of claim 2, wherein forming the all-around source/drain contact comprises:

performing a first selective etching process to remove the portion of the first and second ILDs while maintaining the source/drain epitaxy structure to form ILD trenches that expose the first and second sacrificial regions; and

performing a second selective etching process that removes the first and second sacrificial regions while maintaining the source/drain epitaxy structure to form a source/drain trench; and

filling the ILD trenches and source/drain trench with an electrically conductive material to form the all-around source/drain contact.

4. The method of claim 3, wherein the source/drain trench extends laterally between the ILD trenches and completely beneath the source/drain epitaxy structure.

5. The method of claim 4, wherein filling the source/drain trench forms a lower portion of the all-around source/drain contact, and filling the ILD trenches forms an upper portion and sidewalls of the all-around source/drain contact, the sidewalls extending between the upper portion and the lower portion.

6. The method of claim 5, wherein forming at least one semiconductor nanosheet comprises:

forming, on a buried insulator layer of the semiconductor wafer, a vertical stack of a plurality of sacrificial semiconductor sheets and a plurality of active semiconductor nanosheets in an alternating series arrangement with respect to one another; and

selectively etching the plurality of sacrificial nanosheets while maintaining the active semiconductor nanosheets to form the at least one semiconductor nanosheet being suspended above a portion of the buried insulator layer located in the channel region.

16. The method of claim 1, wherein the electrically conductive material completely surrounds the first and second source/drain epitaxy structures.

7. The method of clam 6, further comprising performing the second selective etching process using an etchant that attacks the sacrificial regions while preserving the buried insulator layer such that the source/drain trench does not extend into the channel region.

8. A method of forming a nanosheet field effect transistor (FET), the method comprising:

forming, on a semiconductor wafer, a nanosheet stack, and forming a gate structure that wraps around a portion of the nanosheet stack to define a channel region of the nanosheet FET;

forming first and second sacrificial regions on the semiconductor substrate, wherein the gate structure is used to self-align the first and second sacrificial regions with respect to sidewalls of the nanosheet stack;

growing, from the first sacrificial region, a first source/drain epitaxy structure that contacts a first side of the nanosheet stack, and growing, from the second sacrificial region, a second source/drain epitaxy structure that contacts an opposing second side of the nanosheet stack; and

replacing the first and second sacrificial regions with an electrically conductive material to form an all-around source/drain contacts that encapsulate the source/drain epitaxy structures.

9. The method of claim 8, wherein replacing the first and second sacrificial regions comprises:

covering the first source/drain epitaxy structure with a first interlayer dielectric (ILD), and covering the second source/drain epitaxy structure with a second ILD; and

replacing the first and second sacrificial regions and a portion of the first and second ILDs with the electrically conductive material to form the all-around source/drain contact.

10. The method of claim 9, wherein forming the all-around source/drain contact comprises:

performing a first selective etching process to remove the portion of the first and second ILDs while maintaining the source/drain epitaxy structure to form ILD trenches that expose the first and second sacrificial regions; and

performing a second selective etching process that removes the first and second sacrificial regions while maintaining the source/drain epitaxy structure to form a source/drain trench; and

filling the ILD trenches and the source/drain trench with the electrically conductive material to form the all-around source/drain contact.

11. The method of claim 10, wherein the source/drain trench extends laterally between the ILD trenches and completely beneath the source/drain epitaxy structure.

12. The method of claim 11, wherein filling the source/drain trench forms a lower portion of the all-around source/drain contact, and filling the ILD trenches forms an upper portion and sidewall portions of the all-around source/drain contact, the sidewall portions extending between the upper portion and the lower portion.

13. The method of claim 12 wherein all of the upper portion, sidewall portions, and lower portion directly contact the source/drain epitaxy structure.

14. The method of claim 8, wherein forming the nanosheet stack further includes forming a vertical stack of a plurality of active semiconductor sheets and a plurality of sacrificial nanosheets in an alternating series arrangement with respect to one another.

15. The method of claim 14, further comprising selectively etching the plurality of sacrificial nanosheets while maintaining the active semiconductor nanosheets to form a channel of the nanosheet FET.