Multi-dimensional computer storage system

• US 10,552,050 B1
• Filed: 04/07/2017
• Issued: 02/04/2020
• Est. Priority Date: 04/07/2017
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Inventors: Verdan, Marlon B., Bruce, Ricardo H.
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US15/482,684
• Time in Patent Office: 1,033 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

In an embodiment of the invention, an apparatus comprises: a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. In another embodiment of the invention, a method comprises: providing a multi-dimensional memory that is expandable in a first direction; wherein the multi-dimensional memory comprises a serial chain; wherein the serial chain comprises a first serial chain that is expandable in a first direction; and wherein the first serial chain comprises a first memory controller, a first memory module coupled to the first memory controller, a second memory controller coupled to the first memory controller, and a second memory module coupled to the second memory controller. Data can be stored into the serial chain, wherein the data is written by a memory transaction from a host.

Claims

1. A storage system, comprising:

a storage system processor connected to a central node of an expandable system bus;

a host interface connected to the central node; and

an expandable memory interface, wherein the expandable memory interface includes;

a plurality of direct memory access (DMA) controllers residing on the expandable system bus, wherein the DMA controllers include a first DMA controller;

a plurality of expandable serial chains, wherein each expandable serial chain includes;

a plurality of nonvolatile memory controllers, including;

a first nonvolatile memory controller directly connected to one of the DMA controllers via a point-to-point link; and

one or more additional nonvolatile memory controllers;

a plurality of nonvolatile memory modules, wherein each nonvolatile memory module is coupled to one of the plurality of nonvolatile memory controllers via a memory bus; and

a serial channel, wherein the serial channel includes a point-to-point connector for each of the one or more additional nonvolatile memory controllers, wherein each point-to-point connector connects a unique pair of the nonvolatile memory controllers; and

a prefetch buffer, wherein the prefetch buffer comprises a buffer set and wherein the buffer set includes one or more buffers, wherein the one or more buffers include at least one of;

a data register of the first nonvolatile memory module, a buffer of the first DMA controller; and

a buffer of the first nonvolatile memory controller;

wherein;

the expandable system bus is configured to accommodate one or more additional DMA controllers residing on the expandable system bus; and

each serial chain is configured to accommodate one or more additional nonvolatile memory controllers.

2. The storage system of claim 1, wherein one or more of the nonvolatile memory modules comprises a flash memory device.

3. The storage system of claim 1, wherein:

each DMA controller is connected to one and only one serial chain.

4. The storage system of claim 1, wherein

two or more expandable serial chains are directly connected to the first DMA controller.

5. The storage system of claim 4, wherein the first DMA controller is configured to select, from the two or more expandable serial chains, an expandable serial chain for performing a memory transaction.

6. The storage system of claim 5, wherein the DMA controller includes a DMA descriptor stored in a memory of the first DMA controller, wherein the DMA descriptor comprises control information to control performance of the memory transaction.

7. The storage system of claim 6, wherein the DMA controller is configured to select the expandable serial chain based at least in part on the DMA descriptor.

8. The storage system of claim 7, wherein the control information includes a point-to-point link identifier that identifies the point-to-point link for the memory transaction.

9. The storage system of claim 7, wherein the control information includes a point-to-point connector identifier indicative of a point-to-point connector for the memory transaction.

10. The storage system of claim 1, wherein the host interface is coupled to a plurality of hosts.

11. The storage system of claim 1, wherein the host interface comprise a first host interface coupled to a first host and wherein the storage system includes a second host interface coupled to a second host.

12. A method, comprising:

receiving, by a storage system, a memory transaction from a host, wherein the storage system comprises;

a storage system processor connected to a central node of an expandable system bus;

a host interface connected to the central node; and

an expandable memory interface, wherein the expandable memory interface includes;

a plurality of direct memory access (DMA) controllers residing on the expandable system bus, wherein the DMA controllers include a first DMA controller;

a plurality of expandable serial chains, wherein each expandable serial chain includes;

a plurality of nonvolatile memory controllers, including;

 

a first nonvolatile memory controller directly connected to one of the DMA controllers via a point-to-point link; and

 

one or more additional nonvolatile memory controllers;

a plurality of nonvolatile memory modules, including a first nonvolatile memory module, wherein each nonvolatile memory module is coupled to one of the plurality of nonvolatile memory controllers via a memory bus; and

a serial channel, wherein the serial channel includes a point-to-point connector for each of the one or more additional nonvolatile memory controllers, wherein each point-to-point connector connects a unique pair of the nonvolatile memory controllers; and

a prefetch buffer, wherein the prefetch buffer comprises a buffer set and wherein the buffer set includes one or more buffers, wherein the one or more buffers include at least one of;

a data register of the first nonvolatile memory module, a buffer of the first DMA controller; and

a buffer of the first nonvolatile memory controller;

wherein;

the expandable system bus is configured to accommodate one or more additional DMA controllers residing on the expandable system bus; and

each serial chain is configured to accommodate one or more additional nonvolatile memory controllers; and

performing, by the storage system, the memory transaction.

13. The method of claim 12, wherein the memory transaction comprises a memory read transaction and wherein performing the memory transaction includes:

performing an internal read operation responsive to determining that data associated with the memory read transaction satisfies a criteria, wherein performing the internal read operation comprises retrieving prefetch data from DB the prefetch buffer; and

sending, to the host, the prefetch data as read data.