Techniques for delegating data processing to a cooperative memory controller
First Claim
1. A memory controller to control flash memory, the flash memory having a plurality of storage locations disposed within structural elements of the flash memory, the memory controller comprising:
- circuitry to control the storage of data in the flash memory in response to a request from a host, the request including a first command, the first command to cause the memory controller to store first data within a first one of the structural elements in the flash memory and to generate second data, the second data being redundancy information which is dependent on the first data; and
a random access memory to receive the second data in association with the first command and to store the second data at an address in the random access memory;
wherein the memory controller is to receive a second command from the host, the second command specifying the address in the random access memory and a destination address within the flash memory, the specified destination address being mapped in advance to a second one of the structural elements to the exclusion of others of the structural elements such that the host selects the second one of the structural elements, the memory controller to responsively transfer the second data from the address in the random access memory to the second one of the structural elements in a manner not requiring intervening transfer of the second data from the random access memory to the host.
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Abstract
Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.
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Citations
23 Claims
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1. A memory controller to control flash memory, the flash memory having a plurality of storage locations disposed within structural elements of the flash memory, the memory controller comprising:
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circuitry to control the storage of data in the flash memory in response to a request from a host, the request including a first command, the first command to cause the memory controller to store first data within a first one of the structural elements in the flash memory and to generate second data, the second data being redundancy information which is dependent on the first data; and a random access memory to receive the second data in association with the first command and to store the second data at an address in the random access memory; wherein the memory controller is to receive a second command from the host, the second command specifying the address in the random access memory and a destination address within the flash memory, the specified destination address being mapped in advance to a second one of the structural elements to the exclusion of others of the structural elements such that the host selects the second one of the structural elements, the memory controller to responsively transfer the second data from the address in the random access memory to the second one of the structural elements in a manner not requiring intervening transfer of the second data from the random access memory to the host. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory device, comprising:
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flash memory having a plurality of storage locations disposed within structural elements of the flash memory; and a memory controller comprising circuitry to control the storage of data in the flash memory in response to a request from a host, the request including a first command, the first command to cause the memory controller to store first data within a first one of the structural elements in the flash memory and to generate second data, the second data being redundancy information which is dependent on the first data, and a random access memory to receive the second data in association with the first command and to store the second data at an address in the random access memory; wherein the memory controller is to receive a second command from the host, the second command specifying the address in the random access memory and a destination address within the flash memory, the specified destination address being mapped in advance to a second one of the structural elements to the exclusion of others of the structural elements, such that the host selects the second one of the structural elements, the memory controller to responsively transfer the second data from the address in the random access memory to the one of the structural elements in a manner not requiring intervening transfer of the second data from the random access memory to the host. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification