Systems and methods for data path power savings in DDR5 memory devices
First Claim
1. A method, comprising:
- transmitting, via an input/output (DQ) pad, a write command to write a memory data incoming from an external system to a bank controller, the bank controller configured to store the memory data in a memory bank;
receiving, via an input/output (I/O) interface circuitry, the write command at a memory device, wherein the I/O interface circuitry is included in the memory device;
converting, via a first one-hot communications interface circuitry of the memory device, a first data pattern of the memory data to be written in the memory bank of the memory device into first one-hot signals based on the write command;
transmitting, via a data path having a data bus of the memory device, the first one-hot signals from the first one-hot communications interface circuitry of the memory device, wherein the first one-hot communications interface circuitry is disposed in the DQ pad, wherein transmitting, via the data path, the first one-hot signals comprises transmitting the first one-hot signals to a first data junction of the memory device, to a single repeater of the memory device, and then from the single repeater to a second data junction of the memory device, wherein the single repeater connects the first data junction to the second data junction and is configured to boost the first one-hot signals to the second data junction;
converting, via a second one-hot communications interface circuitry, the first one-hot signals into the first data pattern, wherein the second one-hot communications interface circuitry is included in the memory bank controller and operatively coupled to the memory bank, and wherein the second one-hot communications interface circuitry is communicatively coupled to the data bus; and
saving the first data pattern in the memory bank, wherein the I/O interface circuitry is communicatively coupled to the memory bank via the first one-hot communications interface circuitry and the second one-hot communications interface circuitry.
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Accused Products
Abstract
A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.
15 Citations
17 Claims
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1. A method, comprising:
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transmitting, via an input/output (DQ) pad, a write command to write a memory data incoming from an external system to a bank controller, the bank controller configured to store the memory data in a memory bank; receiving, via an input/output (I/O) interface circuitry, the write command at a memory device, wherein the I/O interface circuitry is included in the memory device; converting, via a first one-hot communications interface circuitry of the memory device, a first data pattern of the memory data to be written in the memory bank of the memory device into first one-hot signals based on the write command; transmitting, via a data path having a data bus of the memory device, the first one-hot signals from the first one-hot communications interface circuitry of the memory device, wherein the first one-hot communications interface circuitry is disposed in the DQ pad, wherein transmitting, via the data path, the first one-hot signals comprises transmitting the first one-hot signals to a first data junction of the memory device, to a single repeater of the memory device, and then from the single repeater to a second data junction of the memory device, wherein the single repeater connects the first data junction to the second data junction and is configured to boost the first one-hot signals to the second data junction; converting, via a second one-hot communications interface circuitry, the first one-hot signals into the first data pattern, wherein the second one-hot communications interface circuitry is included in the memory bank controller and operatively coupled to the memory bank, and wherein the second one-hot communications interface circuitry is communicatively coupled to the data bus; and saving the first data pattern in the memory bank, wherein the I/O interface circuitry is communicatively coupled to the memory bank via the first one-hot communications interface circuitry and the second one-hot communications interface circuitry. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device, comprising:
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an input/output (DQ) pad configured to transmit memory data incoming from an external system to a bank controller; the bank controller configured to store the memory data in at least one memory bank; a data path comprising a data bus; a first one-hot communications interface circuitry communicatively coupled to the data bus and disposed in the DQ pad; a second one-hot communications interface circuitry communicatively coupled to the data bus and disposed in the bank controller; the at least one memory bank; and an input/output (I/O) interface circuitry communicatively coupled to the at least one memory bank via the first one-hot communications interface circuitry and the second one-hot communications interface circuitry, wherein the first one-hot communications interface circuitry is configured to convert a first data pattern of the memory data received by the I/O interface circuitry into one-hot signals transmitted via the data bus to the second one-hot communications interface circuitry, wherein the second one-hot communications interface circuitry is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank, wherein the I/O interface circuitry includes the first-one hot communications interface circuitry, and wherein the data path comprises a first data junction;
a second data junction communicatively coupled to the at least one memory bank; and
a single repeater connecting the first data junction to the second data junction and configured to boost the one-hot signals from the first data junction to the second data junction, and wherein the one-hot signals are transmitted from the first one-hot communications interface circuitry to the first data junction via the data bus, then to the repeater, and then to the second data junction via the repeater to be stored into the at least one memory bank. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A memory device, comprising:
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a first one-hot communications interface circuitry comprising; a first pumping parallelizer circuitry configured to receive a first data pattern incoming from an input buffer included in an input/output (DQ) pad and to convert the first data pattern into one or more phase-separated nibbles of data, wherein the DQ pad is configured to transmit memory data incoming from an external system to a bank controller, and wherein the bank controller is configured to store the memory data in a memory bank; and a first decoder circuitry configured to receive the one or more phase-separated nibbles of data and configured to decode the one or more phase-separated nibbles of data into first one-hot signals, wherein the first one-hot communications interface circuitry is configured to transmit the first one-hot signals via a data bus for storage of the first data pattern in the memory bank of the memory device, wherein the first one-hot communications interface circuitry is included in an input/output (I/O) interface circuitry of the memory device; a data path comprising the data bus, a first data junction, a second data junction communicatively coupled to the memory bank; and
a single repeater connecting the first data junction to the second data junction, wherein the single repeater is configured to boost the first one-hot signals from the first data junction to the second data junction, wherein the DQ pad includes the first one-hot communications interface circuitry; anda second one-hot communications interface circuitry comprising a first encoder circuit configured to convert the first one-hot signals into the first data pattern for storage of the first data pattern in the memory bank, wherein the second one-hot communications interface circuitry is included in the bank controller. - View Dependent Claims (15, 16, 17)
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Specification