Semiconductor device

• US 10,553,256 B2
• Filed: 12/07/2018
• Issued: 02/04/2020
• Est. Priority Date: 04/30/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ka, Dong Yoon
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/213,796
• Publication Number:
  US 20190333547A1
• Time in Patent Office: 424 Days
• Field of Search: None
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A semiconductor device may include a first column decoder arranged at a first side of a bank, wherein the first column decoder is enabled by a first column decoder select signal. The semiconductor device may include a second column decoder arranged at a second side of the bank, wherein the second column decoder is enabled by a second column decoder select signal; and wherein the bank is arranged between the first column decoder and the second column decoder. The semiconductor device may further include a column decoder selection circuit suitable for activating any one of the first and second column decoder select signals based on a row address.

Claims

1. A semiconductor device comprising:

a first column decoder arranged at a first side of a bank, wherein the first column decoder is enabled by a first column decoder select signal;

a second column decoder arranged at a second side of the bank, wherein the second column decoder is enabled by a second column decoder select signal, and wherein the bank is arranged between the first column decoder and the second column decoder; and

a column decoder selection circuit suitable for activating any one of the first column decoder select signal and the second column decoder select signal based on a row address.

2. The semiconductor device of claim 1 further comprising:

a first column select signal transmission line coupled to the first column decoder, wherein the first column select signal is suitable for transmitting a first column select signal to the bank; and

a second column select signal transmission line coupled to the second column decoder, wherein the second column select signal is suitable for transmitting a second column select signal to the bank.

3. The semiconductor device of claim 2, wherein the first and second column select signal transmission lines each have a length shorter than the height of the bank.

4. The semiconductor device of claim 2, wherein the first and second column select signal transmission lines each have a length half of the height of the bank.

5. The semiconductor device of claim 1, wherein the first column decoder outputs a first column select signal to an upper region of the bank based on a result obtained by decoding a column address.

6. The semiconductor device of claim 1, wherein the second column decoder outputs a second column select signal to a lower region of the bank based on a result obtained by decoding a column address.

7. The semiconductor device of claim 1 further comprising a data input and output (I/O) circuit arranged adjacent to the second column decoder, wherein the second column decoder is arranged between the bank and the I/O circuit, and wherein the I/O circuit is suitable for transmitting data inputted from outside to a data I/O line or outputting data transmitted through the data I/O line to the outside.

8. The semiconductor device of claim 7, wherein the data I/O line corresponds to a bit line of the bank, and wherein the data I/O line is coupled to the data I/O circuit.

9. The semiconductor device of claim 8, wherein the data I/O line has the same length as the height of the bank.

10. The semiconductor device of claim 1, wherein the bank comprises:

a first column selection circuit coupled between a data I/O line and a bit line, wherein the first column selection circuit has a gate terminal coupled to a first column select signal transmission line of the first column decoder, wherein the first column select signal transmission line transmits the first column decoder select signal; and

a second column selection circuit coupled between the data I/O line and the bit line, second column selection circuit has a gate terminal coupled to a second column select signal transmission line of the second column decoder, wherein the second column select signal transmission line transmits the second column decoder select signal.

11. The semiconductor device of claim 1, wherein the column decoder selection circuit enables any one of the first and second column decoders based on a most significant bit (MSB) of the row address.

12. A semiconductor device comprising:

a column decoder selection circuit suitable for activating any one of a first column decoder select signal and a second column decoder select signal based on a row address;

a first column decoder suitable for decoding a column address based on the first column decoder select signal, and for outputting a first column select signal to a first column select signal transmission line based on the decoding result of the column address;

a second column decoder suitable for decoding the column address based on the second column decoder select signal, and for outputting a second column select signal to a second column select signal transmission line based on the decoding result of the column address; and

a bank comprising a plurality of cells coupled to a plurality of word lines and a plurality of bit lines, wherein cells of the plurality of cells in an upper region of the bank are accessed in response to a first column select signal transmitted through the first column select signal transmission line, and wherein cells of plurality of cells in a lower region of the bank are accessed in response to a second column select signal transmitted through the second column select signal transmission line.

13. The semiconductor device of claim 12, wherein the first column decoder is arranged at a first side of the bank, and a second column decoder is arranged at a second side of the bank, wherein the bank is arranged between the first and second column decoders, and wherein the plurality of bit lines extend through the bank between the first and second sides of the bank.

14. The semiconductor device of claim 12, wherein the first and second column select signal transmission lines each have a length shorter than the height of the bank.

15. The semiconductor device of claim 12, wherein the first and second column select signal transmission lines each have a length half of the height of the bank.

16. The semiconductor device of claim 12, further comprising a data input and output (I/O) circuit arranged adjacent to the second column decoder, wherein the second column decoder is arranged between the bank and the I/O circuit.

17. The semiconductor device of claim 16, wherein the data I/O line corresponds to a bit line of the bank, and wherein the data I/O line is coupled to the data I/O circuit.

18. The semiconductor device of claim 17, wherein the data I/O line has the same length as the height of the bank.

19. The semiconductor device of claim 17, wherein the bank comprises:

a first column selection circuit coupled between the data I/O line and a bit line of the plurality of bit lines, wherein the first column selection circuit has a gate terminal coupled to the first column select signal transmission line; and

a second column selection circuit coupled between the data I/O line and the bit line, wherein the second column selection circuit has a gate terminal coupled to the second column select signal transmission line.

20. The semiconductor device of claim 12, wherein the column decoder selection circuit activates any one of the first and second column decoder select signals based on a most significant bit (MSB) of the row address.