Memory cells, memory cell arrays, methods of using and methods of making

• US 10,553,281 B2
• Filed: 07/23/2019
• Issued: 02/04/2020
• Est. Priority Date: 09/03/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/519,515
• Publication Number:
  US 20190355419A1
• Time in Patent Office: 196 Days
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 63/10 : Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

Claims

1. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and

a nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto;

wherein said nonvolatile memory is configured to restore said data to said floating body;

wherein said restore operation is performable to said at least two of said memory cells in parallel.

2. The semiconductor memory array of claim 1, wherein said resistance change element comprises a phase change material.

3. The semiconductor memory array of claim 1, wherein said resistance change element comprises a metal-oxide-metal system.

4. The semiconductor memory array of claim 1, wherein said nonvolatile memory is configured to store said data stored in said floating body upon receiving an instruction to back up said data stored in said floating body.

5. The semiconductor memory array of claim 1, wherein said nonvolatile memory is configured to store said data stored in said floating body upon a loss of power to said array, wherein said array is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory.

6. The semiconductor memory array of claim 5, wherein said loss of power to said array is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

7. The semiconductor memory array of claim 5, wherein, upon restoration of power to said array, said data in said nonvolatile memory is loaded into said floating body and stored therein.

8. The semiconductor memory array of claim 7, wherein said array is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

9. The semiconductor memory array of claim 1, wherein said capacitorless transistor is formed in a fin.

10. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a capacitorless transistor configured to store data as charge therein when power is applied to said memory cell; and

a nonvolatile memory comprising a resistance change element configured to store data stored in said capacitorless transistor upon transfer thereto;

wherein said nonvolatile memory is configured to restore said data to said capacitorless transistor;

wherein charge flow into said capacitorless transistor upon execution of a restore operation to said memory cell depends on charge stored in said resistance change element.

11. The semiconductor memory array of claim 10, wherein said resistance change element comprises a phase change material.

12. The semiconductor memory array of claim 10, wherein said resistance change element comprises a metal-oxide-metal system.

13. The semiconductor memory array of claim 10, wherein said capacitorless transistor comprises a floating body region configured to store a state of said capacitorless transistor.

14. The semiconductor memory array of claim 13, further comprising:

a buried layer region in electrical contact with said floating body region, located below said floating body region.

15. The semiconductor memory array of claim 10, wherein said nonvolatile memory is configured to store said data stored in said capacitorless transistor upon receiving an instruction to back up said data stored in said capacitorless transistor.

16. The semiconductor memory array of claim 10, wherein said nonvolatile memory is configured to store said data stored in said capacitorless transistor upon a loss of power to said memory array, wherein said memory array is configured to perform a shadowing process wherein said data in said capacitorless transistor is loaded into and stored in said nonvolatile memory.

17. The semiconductor memory array of claim 16, wherein said loss of power to said memory array is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

18. The semiconductor memory array of claim 16, wherein, upon restoration of power to said memory array, said data in said nonvolatile memory is loaded into said capacitorless transistor and stored therein.

19. The semiconductor memory array of claim 18, wherein said memory array is configured to reset said nonvolatile memory to an initial state after loading said data into said capacitorless transistor upon said restoration of power.

20. The semiconductor memory array of claim 10, wherein said capacitorless transistor is formed in a fin.

21. The semiconductor memory array of claim 10, wherein said data stored in said capacitorless transistor determines a current flowing to said nonvolatile memory.