MOSFET and memory cell having improved drain current through back bias application

• US 10,553,683 B2
• Filed: 04/27/2016
• Issued: 02/04/2020
• Est. Priority Date: 04/29/2015
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto, Or-Bach, Zvi, Maheshwari, Dinesh
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/724,989
• Publication Number:
  US 20180158912A1
• Time in Patent Office: 1,378 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1083 : with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 : characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 : the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 : with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42356 : Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 19/21 : EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors

Abstract

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Claims

1. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising:

a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a body having said first conductivity type;

a buried layer region interposed between said substrate and said body, wherein a top surface of said buried layer region is lower than a top surface of said body;

a source region and a drain region each having said second conductivity type and being separated by said body; and

said buried layer region separated from said source region and said drain region;

a gate positioned in between said source region and said drain region;

wherein said semiconductor device is configured to function as a memory device upon turning on a bipolar junction transistor (BJT) formed by said buried layer region, said body and one of said source region and said drain region, said memory device having at least two stable states, or as a transistor with increased on-state drain current, upon turning on a lateral bipolar junction (BJT) formed by said source region, said body and said drain region, resulting in increased on-state drain current but with no change in off-state drain current, depending on biases that are applied to said semiconductor device.

2. The semiconductor device of claim 1, wherein whether said semiconductor device functions as said memory device having at least two stable states, or as said transistor with increased on-state drain current, but with no change in off-state drain current is governed by an amount of voltage applied to said buried layer region.

3. The semiconductor device of claim 1, wherein a relatively low voltage applied to said buried layer region governs said semiconductor device to function as a MOSFET (metal-oxide-semiconductor field effect transistor) and wherein a relatively high voltage applied to said buried layer region governs said semiconductor device to function as said memory device having at least two stable states.

4. The semiconductor device of claim 3, wherein a relatively intermediate high voltage applied to said buried layer region higher than said relatively low voltage and lower than said relatively high voltage, but sufficient to turn on said bipolar junction transistor (BJT) formed by said buried layer region, said body and one of said source region and said drain region, turns on said lateral BJT formed by said source region, said body and said drain region, resulting in increased on-state drain current.

5. The semiconductor device of claim 1, wherein at least one of said source region, drain region and buried layer region has a first junction depth less than a second junction depth of at least one other of said source region, drain region and buried layer regions.

6. The semiconductor device of claim 1, further comprising a resistive change element connected to one of said source region or said drain region.