Fully aligned semiconductor device with a skip-level via

• US 10,553,789 B1
• Filed: 10/29/2018
• Issued: 02/04/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lanzillo, Nicholas A., Briggs, Benjamin D., Yang, Chih-Chao, Chen, Hsueh-Chung, Clevenger, Lawrence A.
• Primary Examiner(s): Gebremariam, Samuel A
• Application Number:
  US16/173,234
• Time in Patent Office: 463 Days
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A method includes forming a memory element on a first metal layer. A first cap layer is formed on the first metal layer and sidewalls of the memory element. A first dielectric layer is formed on the first cap layer and a portion of the cap layer on sidewalls of the memory element. A second metal layer is formed on the first dielectric layer. A portion of the memory element is removed and forms an opening. A second cap layer is formed on the top surface of the second metal layer. A second dielectric layer is deposited on the second cap layer and filling the opening. A via is etched in the second dielectric layer exposing a top surface of the memory element. A third metal layer is deposited on the second dielectric layer and filling the via.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a memory element on a first metal layer;

forming a first cap layer on the first metal layer and sidewalls of the memory element;

forming a first dielectric layer on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element;

forming a second metal layer on the first dielectric layer;

planarizing the second metal layer to form a planarized top surface with the first cap layer and the memory element;

selectively removing a portion of the memory element and forming an opening;

selectively depositing a second cap layer on the planarized top surface of the second metal layer;

depositing a second dielectric layer on the second cap layer and filling the opening;

selectively etching a via in the second dielectric layer and exposing a top surface of the memory element; and

depositing a third metal layer on the second dielectric layer and filling the via.

2. The method according to claim 1, wherein the first metal layer is part of an interlevel dielectric (ILD) level which corresponds to a first ILD level.

3. The method according to claim 2, wherein the second metal layer on the first dielectric layer is part of an ILD level which corresponds to a second ILD level.

4. The method according to claim 3, wherein the third metal layer on the second dielectric layer and in the via is part of an ILD level which corresponds to a third ILD level.

5. The method according to claim 1, wherein the first metal layer, the second metal layer and the third metal layer are independently selected from the group consisting of aluminum, tungsten, copper and cobalt.

6. The method according to claim 1, wherein the first cap layer and the second cap layer independently comprise a dielectric cap layer.

7. The method according to claim 1, wherein the first dielectric layer and the second dielectric layer independently comprise a low-k dielectric material or an ultra-low-k dielectric material.

8. The method according to claim 1, wherein the memory element is part of a magnetoresistive random-access memory (MRAM) device and includes a magnetic tunnel junction (MTJ) element formed between a top electrode and a bottom electrode.

9. The method according to claim 8, wherein the step of selectively removing a portion of the memory element comprises selectively removing a portion of the top electrode.

10. The method according to claim 8, wherein the first metal layer, the second metal layer and the third metal layer are the same metal material.

11. The method according to claim 10, wherein the first metal layer, the second metal layer and the third metal layer are selected from the group consisting of aluminum, tungsten, copper and cobalt.

12. The method according to claim 10, wherein the first metal layer is part of an interlevel dielectric (ILD) level which corresponds to a first ILD level.

13. The method according to claim 12, wherein the second metal layer on the first dielectric layer is part of an ILD level which corresponds to a second ILD level.

14. The method according to claim 13, wherein the third metal layer on the second dielectric layer and fills the via is part of an ILD level which corresponds to a third ILD level.

15. The method according to claim 1, wherein the first dielectric layer is a low-k dielectric material comprising silicon oxide, hydrogenated silicon carbon oxide (SiCOH), SiCH or SiCNH.

16. The method according to claim 1, wherein the second dielectric layer is a low-k dielectric material comprising silicon oxide, hydrogenated silicon carbon oxide (SiCOH), SiCH or SiCNH.

17. The method according to claim 1, wherein the first cap layer and the second cap layer independently comprise a nitrogen and hydrogen doped silicon carbide (SiCN(H)) layer, a carbon doped silicon nitride layer, an aluminum nitride (AlN) layer, and a silicon nitride layer.

18. The method according to claim 17, wherein the first metal layer, the second metal layer and the third metal layer are independently selected from the group consisting of aluminum, tungsten, copper and cobalt.

19. The method according to claim 1, wherein the memory element comprises a first electrode and a second electrode.

20. The method according to claim 1, wherein the semiconductor device is a front-end-of-line device.