Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation

• US 10,554,380 B2
• Filed: 01/26/2018
• Issued: 02/04/2020
• Est. Priority Date: 01/26/2018
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Burd, Kevin M
• Application Number:
  US15/881,509
• Publication Number:
  US 20190238308A1
• Time in Patent Office: 739 Days
• Field of Search: 375355
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Claims

1. A method comprising:

receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, each logic branch enabled responsive to a respective input logic combination of the reference clock signal and the phase of the local oscillator signal;

generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments comprising (i) positive weighted segments generated by a first subset of the plurality of logic branches when the reference clock signal and the phase of the local oscillator signal have equal logic levels and (ii) negative weighted segments generated by a second subset of the plurality of logic branches when the reference clock signal and the phase of the local oscillator signal have different logic levels, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, wherein at least two weighted segments of the plurality of weighted segments have different weights;

generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal; and

outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

2. The method of claim 1, wherein each logic branch comprises a plurality of branch segments connected in parallel.

3. The method of claim 2, further comprising generating a phase-control signal comprising a plurality of bits, and wherein each branch segment is enabled according to a respective bit of the plurality of bits of the phase-control signal.

4. The method of claim 3, wherein each branch segment is enabled according to a corresponding enabling transistor receiving the respective bit as an input.

5. The method of claim 3, wherein generating the phase-control signal comprises selecting a value corresponding to the phase offset from a lookup table.

6. The method of claim 2, wherein the respective weight for a given weighted segment is determined by a number of branch segments enabled in the logic branch.

7. The method of claim 1, wherein the respective weight for a given weighted segment is determined in part by transistor dimensions in the logic branch.

8. The method of claim 1, wherein the respective weight for a given weighted segment is determined in part by a tunable impedance connected to the logic branch.

9. The method of claim 1, wherein the aggregate control signal is further generated based on weighted segments in a second phase-error signal generated using the reference clock signal and a second phase of the local oscillator signal that is adjacent to the phase of the local oscillator signal.

10. The method of claim 9, wherein the first and second phase-error signals are generated using sets of inversely-enabled branch segments.

11. An apparatus comprising:

a plurality of logic branches of a dynamically-weighted XOR gate, the plurality of logic branches configured to receive a reference clock signal and a phase of a local oscillator signal and to responsively generate a plurality of weighted segments of a phase-error signal, each weighted segment of the phase-error signal generated by a corresponding logic branch enabled responsive to a respective input logic combination of the reference clock and the phase of the local oscillator and having a respective weight selectively applied by a corresponding logic branch of the plurality of logic branches, wherein at least two weighted segments of the plurality of weighted segments have different weights, the plurality of logic branches comprising;

a first subset of the plurality of logic branches configured to generate positive weighted segments when the reference clock signal and the phase of the local oscillator signal have equal logic levels;

a second subset of the plurality of logic branches configured to generate negative weighted segments when the reference clock signal and the phase of the local oscillator signal have different logic levels; and

a common node connected to the plurality of logic branches configured to generate an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and to responsively output the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

12. The apparatus of claim 11, wherein each logic branch comprises a plurality of branch segments connected in parallel.

13. The apparatus of claim 12, further comprising a phase interpolator control signal generator configured to generate a phase-control signal comprising a plurality of bits, and wherein each branch segment is enabled according to a respective bit of the plurality of bits of the phase-control signal.

14. The apparatus of claim 13, wherein each branch segment comprises a corresponding enabling transistor configured to receive the respective bit as an input.

15. The apparatus of claim 13, wherein the phase interpolator control signal generator is configured to generate the phase-control signal by selecting a value corresponding to the phase offset from a lookup table.

16. The apparatus of claim 12, wherein the respective weight for a given weighted segment is determined by a number of branch segments enabled in the logic branch.

17. The apparatus of claim 11, wherein the respective weight for a given weighted segment is determined in part by transistor dimensions in the logic branch.

18. The apparatus of claim 11, wherein the respective weight for a given weighted segment is determined in part by a tunable impedance connected to the logic branch.

19. The apparatus of claim 11, wherein the aggregate control signal is further generated based on weighted segments in a second phase-error signal generated using the reference clock signal and a second phase of the local oscillator signal that is adjacent to the phase of the local oscillator signal.

20. The apparatus of claim 19, wherein the first and second phase-error signals are generated using sets of inversely-enabled branch segments.