Semiconductor device and security system

• US 10,554,422 B2
• Filed: 09/20/2017
• Issued: 02/04/2020
• Est. Priority Date: 09/20/2016
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yano, Masaru
• Primary Examiner(s): Holder, Bradley W
• Application Number:
  US15/710,358
• Publication Number:
  US 20180083788A1
• Time in Patent Office: 867 Days
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H04L 9/3226 using a predetermined code, e.g. password, passphrase or PIN network architectures or network communication protocols for supporting authentication of entities using passwords in a packet data network H04L63/083
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]
• CPC Class Codes: H04L 9/34 Bits, or blocks of bits, of the telegraphic message being interchanged in time for speech signals H04K1/06

Abstract

A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Claims

1. A semiconductor device comprising:

a unique-information generation circuit configured to operate in a plurality of operation environments to generate unique information, wherein the unique information comprises stable information and unstable information, the stable information is a constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments;

a controlling logic configured to detect the unstable information and generate code information based on the detected unstable information, wherein the code information comprises a code sequence formed by the stable information and the unstable information and identification information used to identify the unstable information of the code sequence;

a memory portion storing the code information,

wherein the controlling logic reads out the code information from the memory portion and outputs the code information to a host device;

wherein the memory portion stores the code information and the identification information in a region designated by addresses, and the addresses are stored in a configuration register.

2. The semiconductor device according to claim 1,

wherein the controlling logic is further configured to delete the code information and the identification information which are stored in the memory portion.

3. The semiconductor device according to claim 2, wherein the controlling logic deletes the code information and the identification information in response to a request from the host device.

4. The semiconductor device according to claim 2, wherein after the controlling logic deletes the code information and the identification information, the controlling logic outputs the unique information generated by the unique-information generation circuit to the host device when the host device requests the unique information.

5. The semiconductor device according to claim 1, wherein the plurality of operation environments comprises operations in different operation temperatures, different supply voltages, or combination thereof.

6. The semiconductor device according to claim 1, wherein a value included in a selected bit in the stable information is “

0”

or “

1”

in all of the plurality of operation environments, and a value included in a selected bit in the unstable information changes between “

0” and

“

1”

in the plurality of operation environments.

7. The semiconductor device according to claim 1,

wherein the controlling logic is further configured to determine whether the semiconductor device operates in the plurality of operation environments,

wherein the controlling logic is further configured to acquire the unique information from the unique-information generation circuit when the controlling logic determines that the semiconductor device operates in the plurality of operation environments.

8. The semiconductor device according to claim 1, wherein the unique-information generation circuit comprises:

n sets of inverter circuits, each of the n sets of inverter circuits comprising one pair of inverters,

n sets of comparators, each of the n sets of comparators compares output voltages output by the one pair of inventers in one of the n-sets of inverter circuits; and

an encoder circuit configured to receive comparison results of the n sets of comparators to generate the unique information having n bits.

9. The semiconductor device according to claim 8, wherein a voltage whose level is half of a level of a power supply voltage is supplied to gates of the one pair of inventers in one of the n-sets of inverter circuits.