Communication between threads of multi-thread processor
First Claim
1. A method in a microprocessor, comprising:
- allocating a set of mailbox registers to each thread of a plurality of threads for execution in the microprocessor;
including, in a field of a mailbox register in the set of mailbox registers, an identifier of a next thread of the plurality of threads to be executed in the microprocessor upon thread switching;
switching execution of the thread to execution of the next thread based upon a thread switch condition indicated in the mailbox register and the identifier of the next thread;
setting a bit in a first field of a thread enable register to enable a corresponding thread of the plurality of threads in a simultaneous multithreading (SMT) mode, the corresponding thread enabling one or more other threads of the plurality of threads in the SMT mode; and
enabling or disabling a thread of each of the plurality of threads for coarse grain multithreading, based on a corresponding bit in a second field of the thread enable register.
1 Assignment
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Accused Products
Abstract
Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The thread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.
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Citations
27 Claims
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1. A method in a microprocessor, comprising:
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allocating a set of mailbox registers to each thread of a plurality of threads for execution in the microprocessor; including, in a field of a mailbox register in the set of mailbox registers, an identifier of a next thread of the plurality of threads to be executed in the microprocessor upon thread switching; switching execution of the thread to execution of the next thread based upon a thread switch condition indicated in the mailbox register and the identifier of the next thread; setting a bit in a first field of a thread enable register to enable a corresponding thread of the plurality of threads in a simultaneous multithreading (SMT) mode, the corresponding thread enabling one or more other threads of the plurality of threads in the SMT mode; and enabling or disabling a thread of each of the plurality of threads for coarse grain multithreading, based on a corresponding bit in a second field of the thread enable register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A microprocessor, comprising:
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a set of mailbox registers allocated to each thread of a plurality of threads for execution in the microprocessor; and one or more auxiliary registers allocated to one or more of the plurality of threads including a thread enable register allocated to the plurality of threads, wherein a mailbox register in the set of mailbox registers allocated to that thread comprises an identifier of a next thread of the plurality of threads to which that thread switches based on a thread switch condition indicated in the mailbox register, the one or more auxiliary registers configure at least one of;
a number of threads in the plurality of threads for execution in the microprocessor, a priority for thread switching, storing a program counter (PC) of each thread, or storing states of registers of each thread,a bit in a first field of the thread enable register is set to enable a corresponding thread of the plurality of threads in a simultaneous multithreading (SMT) mode, the corresponding thread enabling one or more other threads of the plurality of threads for execution in the SMT mode, and a thread of each of the plurality of threads is enabled or disabled for coarse grain multithreading, based on a corresponding bit in a second field of the thread enable register. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification