Restricted instructions in transactional execution

• US 10,558,465 B2
• Filed: 12/08/2017
• Issued: 02/11/2020
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Greiner, Dan F., Jacobi, Christian, Slegel, Timothy J.
• Primary Examiner(s): Metzger, Michael J
• Application Number:
  US15/836,019
• Publication Number:
  US 20180101386A1
• Time in Patent Office: 795 Days
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.

Claims

1. A computer-implemented method of performing processing associated with transactional execution in a computing environment, the computer-implemented method comprising:

obtaining, by a processor, an instruction to be executed as part of a transaction of a nest of transactions;

computing one or more effective controls from one or more controls set by one or more transaction begin instructions initiating one or more transactions of the nest of transactions, the one or more effective controls comprising an effective allow floating point operation control that indicates whether specified floating point instructions are permitted to be executed;

determining by the processor whether the instruction is a selectively restricted instruction that is prohibited from execution within the transaction, the determining being based on the one or more effective controls computed from the one or more controls set by the one or more transaction begin instructions; and

performing processing associated with the instruction based on whether the instruction is selectively restricted.

2. The computer-implemented method of claim 1, further comprising executing a plurality of transaction begin instructions to initiate a plurality of transactions, the plurality of transactions creating the nest of transactions and including the one or more transactions.

3. The computer-implemented method of claim 1, wherein the one or more transaction begin instructions comprise multiple transaction begin instructions, and wherein the computing comprises determining a value for the effective allow floating point operation control, the determining the value comprising performing a logical AND of allow floating point operation controls of the multiple transaction begin instructions.

4. The computer-implemented method of claim 1, wherein the performing comprises aborting the transaction based on the instruction being selectively restricted.

5. The computer-implemented method of claim 4, wherein based on aborting the transaction, storing an abort code in a transaction diagnostic block identified by one transaction begin instruction of the one or more transaction begin instructions and setting a condition code.

6. The computer-implemented method of claim 1, wherein the performing comprises executing the instruction based on the determining indicating the instruction is not selectively restricted.

7. The computer-implemented method of claim 1, wherein the one or more effective controls further comprise an effective allow access register modification control that indicates whether an access register is permitted to be modified.

8. The computer-implemented method of claim 1, wherein based on the instruction being selectively restricted, the instruction is restricted for one transaction but not restricted for another transaction.

9. The computer-implemented method of claim 1, further comprising obtaining another instruction to be executed in the transaction and checking whether the other instruction is a restricted instruction for transactional processing, wherein the performing processing aborts the transaction based on the other instruction being restricted.

10. The computer-implemented method of claim 9, further comprising determining whether the transaction is a constrained transaction or a nonconstrained transaction, and wherein the checking whether the other instruction is restricted is based on whether the transaction is constrained or nonconstrained.