Cache controller for non-volatile memory

• US 10,558,569 B2
• Filed: 10/31/2013
• Issued: 02/11/2020
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Boehm, Hans, Chakrabarti, Dhruva
• Primary Examiner(s): Faal, Baboucarr
• Application Number:
  US15/031,805
• Publication Number:
  US 20160246724A1
• Time in Patent Office: 2,294 Days
• Field of Search: None
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Claims

1. A method comprising:

monitoring, using a data structure storing address tags of dirty cache lines, a quantity of the dirty cache lines in a cache that includes cache lines storing data and respective address tags, the dirty cache lines corresponding to data in a main memory;

computing, by a cache controller or a processor, a threshold that is based on a capacity of the data structure and that is less than a cache line storage capacity of the cache wherein computing the threshold comprises adjusting the threshold by the cache controller or the processor based on a frequency of cache flushes from the cache to the main memory;

comparing the quantity of the dirty cache lines to the threshold; and

causing a write back by the cache controller of at least one of the dirty cache lines to the main memory in response to a store event that causes the quantity of the dirty cache lines to satisfy the threshold.

2. The method of claim 1, wherein the store event does not cause the quantity of the dirty cache lines to increase toward the threshold if the store event modifies a dirty cache line in the cache.

3. The method of claim 1, further comprising:

mapping a read-only memory address space and a writable memory address space; and

in response to the store event comprising a store instruction to the read-only memory address space, producing a store-with-tracking instruction to the writable memory address space, the store-with-tracking instruction causing tracking, in the data structure, of a dirty cache line created by the store event by writing an address tag of the store event to the data structure.

4. The method of claim 1, further comprising, in response to processor resources being available, selecting a further dirty cache line of the dirty cache lines to be written back to the main memory using a background process before the quantity of the dirty cache lines satisfies the threshold.

5. The method of claim 1, wherein the quantity of the dirty cache lines satisfies the threshold if the quantity of the dirty cache lines is greater than or equal to the threshold.

6. The method of claim 1, wherein the data structure comprises a hash table comprising locations that map to corresponding address tags, the locations of the hash table comprising entries storing the address tags of the dirty cache lines.

7. The method of claim 1, further comprising:

receiving a further store event that includes a first address tag that maps to an entry of the data structure; and

in response to detecting that the entry already stores a second address tag, causing a write back by the cache controller of a dirty cache line corresponding to the second address tag from the cache to the main memory.

8. The method of claim 1, wherein each address tag of the address tags stored in the data structure comprises a portion of a respective memory address corresponding to a location of the main memory.

9. The method of claim 1, wherein adjusting the threshold comprises increasing, by the cache controller or the processor, the threshold based on determining that the frequency of cache flushes from the cache to the main memory has decreased.

10. A non-transitory machine readable storage medium comprising instructions that, when executed, cause a machine to:

monitor, using a data structure storing address tags of dirty cache lines, a quantity of the dirty cache lines in a cache that includes cache lines storing data and respective address tags, the dirty cache lines corresponding to data in a main memory;

compute a threshold that is based on a capacity of the data structure and that is less than a cache line storage capacity of the cache, wherein computing the threshold comprises adjusting the threshold by the machine based on a frequency of cache flushes from the cache to the main memory;

compare the quantity of the dirty cache lines to the threshold that is based on the capacity of the data structure and that is less than the cache line storage capacity of the cache; and

cause a write back of at least one of the dirty cache lines to the main memory in response to a store event that causes the quantity of the dirty cache lines to satisfy the threshold.

11. The non-transitory machine readable storage medium of claim 10, wherein the store event does not cause the quantity of the dirty cache lines to increase toward the threshold if the store event modifies a dirty cache line.

12. The non-transitory machine readable storage medium of claim 10, wherein the instructions, when executed cause the machine to:

map a read-only memory address space and a writable memory address space; and

in response to the store event comprising a store instruction to the read-only memory address space, produce a store-with-tracking instruction to the writable memory address space, the store-with-tracking instruction causing tracking, in the data structure, of a dirty cache line created by the store event by writing an address tag of the store event to the data structure.

13. The non-transitory machine readable storage medium of claim 10, wherein the data structure is a hash table separate from the cache, the hash table comprising locations that map to corresponding address tags.

14. The non-transitory machine readable storage medium of claim 12, wherein the producing is performed as part of trapping the store instruction of the store event.

17. The non-transitory machine readable storage medium of claim 10, herein adjusting the threshold comprises increasing, by the machine, the threshold based on determining that the frequency of cache flushes from the cache to the main memory has decreased.

15. An integrated circuit comprising:

a dirty address updater to;

monitor, using a data structure storing address tags of dirty cache lines, a quantity of the dirty cache lines in a cache that includes cache lines storing data and respective address tags, the dirty cache lines storing data to be written back to a non-volatile memory,

adjust a threshold that is based on a capacity of the data structure and that is less than a cache line storage capacity of the cache, wherein adjusting the threshold is further based on a frequency of cache flushes from the cache to the non-volatile memory, and

compare the quantity of the dirty cache lines to the threshold; and

a flush indicator to cause a write back of at least one of the dirty cache lines to the non-volatile memory in response to a store event that causes the quantity of the of dirty cache lines to satisfy the threshold.

16. The integrated circuit of claim 15, wherein the store event does not cause the quantity of the dirty cache lines to increase if the store event modifies a dirty cache line.

18. The integrated circuit of claim 15, wherein the dirty address updater is to receive a further store event that includes a first address tag that maps to an entry of the data structure, and

wherein the flush indicator is to, in response to detecting that the entry already stores a second address tag, cause a write back by a cache controller of a dirty cache line corresponding to the second address tag from the cache to the non-volatile memory.

19. The integrated circuit of claim 18, wherein the data structure comprises a hash table comprising locations that map to corresponding address tags.