Communication interface transaction security

• US 10,558,604 B2
• Filed: 12/20/2017
• Issued: 02/11/2020
• Est. Priority Date: 12/20/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chun, Christopher Kong Yee, Rosolowski, Chris
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US15/849,459
• Publication Number:
  US 20190188175A1
• Time in Patent Office: 783 Days
• Field of Search: 710240-244
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Claims

1. A method of providing communications in an apparatus, comprising:

monitoring a communication interface arbitration sequence on a system bus having only a clock signal line and a data signal line, wherein the arbitration sequence includes a plurality of master priority level slots;

detecting a master priority level within the monitored arbitration sequence based on a master priority level slot of the plurality of master priority slots in which a master drives the data signal line for sending a transaction on the system bus;

using the determined master priority level to determine a master identifier of the master that is sending the transaction on the system bus; and

processing the transaction based on the determined master identifier of the master that is sending the transaction.

2. The method of claim 1, wherein processing the transaction includes allowing or blocking the transaction based on the determined master identifier of the master that is sending the transaction.

3. The method of claim 2, wherein allowing the transaction includes comparing the determined master identifier to a defined set of authorized master identifiers.

4. The method of claim 2, wherein blocking the transaction includes comparing the determined master identifier to a defined set of unauthorized master identifiers.

5. The method of claim 1, wherein the communication interface arbitration sequence includes a power management interface arbitration sequence.

6. An integrated circuit comprising:

a processor to;

monitor a communication interface arbitration sequence on a system bus having only a clock signal line and a data signal line, wherein the arbitration sequence includes a plurality of master priority level slots;

detect a master priority level within the monitored arbitration sequence based on a master priority level slot of the plurality of master priority slots in which a master drives the data signal line for sending a transaction on the system bus;

use the determined master priority level to determine a master identifier of the master that is sending the transaction on the system bus; and

process the transaction based on the determined master identifier of the master that is sending the transaction.

7. The integrated circuit of claim 6, wherein the processor to process the transaction includes to allow or block the transaction based on the determined master identifier of the master that is sending the transaction.

8. The integrated circuit of claim 7, wherein the processor to allow the transaction includes to compare the determined master identifier to a defined set of authorized master identifiers.

9. The integrated circuit of claim 7, wherein the processor to block the transaction includes to compare the determined master identifier to a defined set of unauthorized master identifiers.

10. The integrated circuit of claim 6 wherein the communication interface arbitration sequence includes a power management interface arbitration sequence.

11. A computing device comprising:

means for monitoring a communication interface arbitration sequence on a system bus having only a clock signal line and a data signal line, wherein the arbitration sequence includes a plurality of master priority level slots;

means for detecting a master priority level within the monitored arbitration sequence based on a master priority level slot of the plurality of master priority slots in which a master drives the data signal line for sending a transaction on the system bus;

means for determining, using the determined master priority level, a master identifier of the master that is sending the transaction on the system bus; and

means for processing the transaction based on the determined master identifier of the master that is sending the transaction.

12. The computing device of claim 11, wherein the means for processing the transaction includes means for allowing or blocking the transaction based on the determined master identifier of the master that is sending the transaction.

13. The computing device of claim 12, wherein the means for allowing the transaction includes means for comparing the determined master identifier to a defined set of authorized master identifiers.

14. The computing device of claim 12, wherein the means for blocking the transaction includes means for comparing the determined master identifier to a defined set of unauthorized master identifiers.

15. The computing device of claim 11, wherein the communication interface arbitration sequence includes a power management interface arbitration sequence.

16. A non-transitory, computer-readable medium, having stored thereon computer-readable instructions for providing communications, comprising instructions configured to cause an apparatus to:

monitor a communication interface arbitration sequence on a system bus having only a clock signal line and a data signal line, wherein the arbitration sequence includes a plurality of master priority level slots;

detect a master priority level within the monitored arbitration sequence based on a master priority level slot of the plurality of master priority slots in which a master drives the data signal line for sending a transaction on the system bus;

use the determined master priority level to determine a master identifier of the master that is sending the transaction on the system bus; and

process the transaction based on the determined master identifier of the master that is sending the transaction.

17. The non-transitory, computer-readable medium of claim 16, wherein to process the transaction includes to allow or block the transaction based on the determined master identifier of the master that is sending the transaction.

18. The non-transitory, computer-readable medium of claim 17, wherein to allow the transaction includes to compare the determined master identifier to a defined set of authorized master identifiers.

19. The non-transitory, computer-readable medium of claim 17, wherein to block the transaction includes to compare the determined master identifier to a defined set of unauthorized master identifiers.

20. The non-transitory, computer-readable medium of claim 16, wherein the communication interface arbitration sequence includes a power management interface arbitration sequence.