Pixel driver circuitry for a display device

• US 10,559,256 B2
• Filed: 11/13/2018
• Issued: 02/11/2020
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Lee, Kuan-Feng, Wu, Yu-Hsien
• Primary Examiner(s): Amadiz, Rodney
• Application Number:
  US16/189,458
• Publication Number:
  US 20190080649A1
• Time in Patent Office: 455 Days
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A display device includes at least one first emitting diode coupled with an input node; and a pixel driver circuitry including a drive transistor including a first terminal and a control terminal, wherein the first terminal is coupled with the input node; a data input transistor including a second terminal coupled with the control terminal; a reset transistor including a first gate, a second gate, a semiconductor layer and a third terminal coupled with the input node, wherein, in a cross-sectional view of the display device, the first gate and the second gate are disposed on the same side of the semiconductor layer.

Claims

1. A display device comprising:

at least one first emitting diode coupled with an input node; and

a pixel driver circuitry comprising;

a drive transistor comprising a first terminal and a control terminal, wherein the first terminal is coupled with the input node;

a data input transistor comprising a second terminal coupled with the control terminal;

a reset transistor comprising a first gate, a second gate, a semiconductor layer and a third terminal coupled with the input node,

wherein, in a cross-sectional view of the display device, the first gate and the second gate are disposed on the same side of the semiconductor layer.

2. The display device as claimed in claim 1, wherein the semiconductor layer of the reset transistor comprises a low temperature poly-silicon (LTPS) semiconductor material.

3. The display device as claimed in claim 1, wherein a closed area is formed between the first gate, the second gate, and the semiconductor layer in a top view of the display device.

4. The display device as claimed in claim 1, further comprising an active region and a gate driver region arranged outside the active region, wherein the pixel driver circuitry is within the active region;

wherein at least one the semiconductor layer of a plurality of transistors in the gate driver region comprises an LTPS semiconductor material.

5. The display device as claimed in claim 4, wherein the gate driver region at least partially overlaps a planarization layer of the display device in a top view of the display device.

6. The display device as claimed in claim 4, further comprising a conductive ring;

wherein the gate driver region comprises a gate driver circuitry, and the conductive ring at least partially overlaps the gate driver circuitry of the gate driver region in a top view of the display device.

7. The display device as claimed in claim 4, wherein the gate driver region comprises a conductive ring coupled with a conductive layer of the active region.

8. The display device as claimed in claim 4, further comprising a pixel define layer;

wherein the pixel define layer is disposed between a conductive ring of the gate driver region and a conductive layer of the active region in the cross-sectional view of the display device.

9. The display device as claimed in claim 1, wherein a source/drain terminal of the drive transistor is disposed on a source/drain terminal of the data input transistor in the cross-sectional view of the display device.

10. The display device as claimed in claim 1, further comprising a storage capacitor;

wherein the storage capacitor at least partially overlaps the first emitting diode in a top view of the display device.

11. The display device as claimed in claim 1, further comprising a passivation layer;

wherein an upper surface of the first emitting diode is higher than that of the passivation layer in the cross-sectional view of the display device.

12. The display device as claimed in claim 1, wherein a semiconductor layer of the data input transistor comprises an oxide semiconductor material.

13. The display device as claimed in claim 1, further comprising a conductive connection that couples with a source/drain terminal of the reset transistor having a reference voltage.

14. The display device as claimed in claim 13, further comprising another conductive connection that couples with a supply voltage (VDD) to a fourth terminal of an emission transistor.

15. The display device as claimed in claim 1, wherein the first light emitting diode is coupled with the input node via a conductive layer that at least partially overlaps a planarization layer or a pixel define layer in a top view of the display device.

16. The display device as claimed in claim 1, further comprising a conductive connection that couples with a source/drain terminal of the data input transistor having an input data signal (Data).

17. The display device as claimed in claim 1, further comprising an active region and a gate driver region arranged outside the active region, wherein the drive transistor, the data input transistor, and the reset transistor are arranged within the active region.

18. The display device as claimed in claim 17, further comprising a gate driver circuitry, wherein the gate driver circuitry is arranged within the gate driver region.