Method for operating the semiconductor device

• US 10,559,341 B2
• Filed: 01/24/2017
• Issued: 02/11/2020
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ishizu, Takahiko, Tamura, Hikaru
• Primary Examiner(s): Bertram, Ryan
• Assistant Examiner(s): Ta, Trang K
• Application Number:
  US15/414,085
• Publication Number:
  US 20170221547A1
• Time in Patent Office: 1,113 Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations

Abstract

A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.

Claims

1. A method for operating a semiconductor device comprising a CPU core, a first memory cell, and a second memory cell, the method comprising:

a first step of writing a first data read by the CPU core from a region where the first data is held to the first memory cell;

a second step of executing a program in the CPU core;

a third step of interrupting the program in the CPU core;

a fourth step of reading a second data from the first memory cell;

a fifth step of comparing the first data read again by the CPU core from the region where the first data is held with the second data in the CPU core so as to determine whether the first data written in the first step deteriorates, and

a sixth step of performing a refresh operation on the first memory cell and the second memory cell and performing the second step,

wherein the second step is performed after the fifth step in the case where the first data matches the second data in the fifth step,

wherein the sixth step is performed after the fifth step in the case where the first data does not match the second data in the fifth step,

wherein the first memory cell comprises a first capacitor, and

wherein the second memory cell comprises a second capacitor.

2. The method according to claim 1,

wherein capacitance of the first capacitor is smaller than capacitance of the second capacitor.

3. The method according to claim 1,

wherein the first memory cell comprises at least one of a first transistor and a third transistor,

wherein the second memory cell comprises at least one of a second transistor and a fourth transistor,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, and the fourth transistor independently comprises an oxide semiconductor comprising at least one of indium, an element M, and zinc, and

wherein the element M is aluminum, gallium, yttrium, or tin.

4. The method according to claim 3,

wherein the first transistor is used as a write transistor, and

wherein the second transistor is used as a write transistor.

5. The method according to claim 3,

wherein the third transistor is used as a read transistor, and

wherein the fourth transistor is used as a read transistor.

6. An electronic device comprising:

the semiconductor device that uses the method according to claim 1; and

a housing.

7. A method for operating a semiconductor device comprising a CPU core, a first memory cell, and a second memory cell, the method comprising:

writing a first data read by the CPU core from a region where the first data is held to the first memory cell;

executing a program in the CPU core;

interrupting the program in the CPU core;

reading a second data that is based on the first data from the first memory cell;

comparing the first data read again by the CPU core from the region where the first data is held with the second data in the CPU core so as to determine whether the first data written to the first memory cell deteriorates;

returning to the execution of the program again in the case where the first data matches the second data in the comparison; and

performing a refresh operation on the first memory cell and the second memory cell in the case where the first data does not match the second data in the comparison,

wherein the first memory cell comprises a first capacitor, and

wherein the second memory cell comprises a second capacitor.

8. The method according to claim 7,

wherein capacitance of the first capacitor is smaller than capacitance of the second capacitor.

9. The method according to claim 7,

wherein the first memory cell comprises at least one of a first transistor and a third transistor,

wherein the second memory cell comprises at least one of a second transistor and a fourth transistor,

wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, and the fourth transistor independently comprises an oxide semiconductor comprising at least one of indium, an element M, and zinc, and

wherein the element M is aluminum, gallium, yttrium, or tin.

10. The method according to claim 9,

wherein the first transistor is used as a write transistor, and

wherein the second transistor is used as a write transistor.

11. The method according to claim 9,

wherein the third transistor is used as a read transistor, and

wherein the fourth transistor is used as a read transistor.

12. An electronic device comprising:

the semiconductor device that uses the method according to claim 7; and

a housing.