Dynamic random access memory with reduced power consumption

• US 10,559,342 B2
• Filed: 08/24/2018
• Issued: 02/11/2020
• Est. Priority Date: 06/14/2018
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Fujioka, Shinya, Ikeda, Hitoshi
• Primary Examiner(s): Auduong, Gene N
• Application Number:
  US16/111,227
• Publication Number:
  US 20190385668A1
• Time in Patent Office: 536 Days
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Claims

1. A dynamic random access memory, comprising:

a temperature sensor, sensing an operating temperature of the dynamic random access memory;

a dynamic memory cell array;

a control circuit, coupled to the dynamic memory cell array, and accessing and managing the dynamic memory cell array;

a plurality of power supply circuits, supplying power to the dynamic memory cell array and the control circuit; and

a power control circuit, controlling power outputs of the power supply circuits,

wherein when the dynamic random access memory enters a self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the dynamic random access memory,

wherein in case that the dynamic random access memory is in the self-refresh mode, when the operating temperature of the dynamic random access memory is higher than a threshold temperature, the power control circuit is operated in the normal power control state, and when the operating temperature of the dynamic random access memory is lower than the threshold temperature, the power control circuit is operated in the low power control state.

2. The dynamic random access memory as claimed in claim 1, wherein in case that the power control circuit is operated in the low power control state, the power control circuit determines whether to leave the low power control state to enter the normal power control state according to the operating temperature of the dynamic random access memory.

3. The dynamic random access memory as claimed in claim 1, wherein in case that the power control circuit is operated in the normal power control state, the power control circuit determines whether to leave the normal power control state to enter the low power control state according to the operating temperature of the dynamic random access memory.

4. The dynamic random access memory as claimed in claim 1, wherein the power supply circuits are divided into a plurality of groups, and the groups comprise a first group,

when the power control circuit is operated in the low power control state, and during an internal self-refresh command sending period, the power control circuit controls the power outputs of the power supply circuits of the first group to switch from a floating state to an active state, and

when the power control circuit is operated in the low power control state, and after the internal self-refresh command sending period is ended, the power control circuit controls the power outputs of the power supply circuits of the first group to switch back from the active state to the floating state.

5. The dynamic random access memory as claimed in claim 4, wherein when the power control circuit is operated in the normal power control state, the power control circuit controls the power outputs of the power supply circuits of the first group to maintain the active state.

6. The dynamic random access memory as claimed in claim 4, wherein the groups comprise a second group,

when the power control circuit is operated in the low power control state, the power control circuit controls the power outputs of the power supply circuits of the second group to switch from the active state to the floating state, and

when the power control circuit is operated in the normal power control state, the power control circuit controls the power outputs of the power supply circuits of the second group to switch back from the floating state to the active state.

7. The dynamic random access memory as claimed in claim 6, wherein the groups comprise a third group,

when the power control circuit is operated in the low power control state, the power control circuit controls the power outputs of the power supply circuits of the third group to clamp to a ground voltage, and

when the power control circuit is operated in the normal power control state, the power control circuit controls the power outputs of the power supply circuits of the third group to restore the active state.

8. The dynamic random access memory as claimed in claim 7, wherein the groups comprise a fourth group,

when the power control circuit is operated in the low power control state, the power control circuit controls the power outputs of the power supply circuits of the fourth group to maintain the active state, and

when the power control circuit is operated in the normal power control state, the power control circuit controls the power outputs of the power supply circuits of the fourth group to maintain the active state.

9. The dynamic random access memory as claimed in claim 1, wherein the control circuit comprises:

an input-output circuit, configured to provide an access interface to an external device, wherein the power supply circuits comprise an input-output power supply circuit to supply power to the input-output circuit, when the power control circuit is operated in the low power control state, a power output of the input-output power supply circuit is maintained to a floating state, and when the power control circuit is operated in the normal power control state, the power output of the input-output power supply circuit is switched back from the floating state to an active state; and

a peripheral circuit, coupled between the input-output circuit and the dynamic memory cell array, wherein the peripheral circuit manages the power control circuit by sending at least one internal command, the at least one internal command comprises an internal self-refresh command, a self-refresh entry command or a self-refresh exit command, the power supply circuits further comprise a peripheral power supply circuit for supplying power to the peripheral circuit, and when the power control circuit is operated in the low power control state and the normal power control state, a power output of the peripheral power supply circuit is all maintained to the active state.

10. The dynamic random access memory as claimed in claim 1, wherein the power supply circuits further comprise a first memory cell power supply circuit, a second memory cell power supply circuit, a third memory cell power supply circuit, a first sensing amplifier power supply circuit, a second sensing amplifier power supply circuit and a third sensing amplifier power supply circuit for supplying power to the dynamic memory cell array,

the first memory cell power supply circuit and the third sensing amplifier power supply circuit belong to the first group;

when the power control circuit is operated in the low power control state, a power output of the first sensing amplifier power supply circuit is switched to the floating state, power outputs of the second memory cell power supply circuit and the third memory cell power supply circuit are clamped to a ground voltage, and a power output of the second sensing amplifier power supply circuit is maintained to the active state; and

when the power control circuit is operated in the normal power control state, power outputs of the first sensing amplifier power supply circuit, the second sensing amplifier power supply circuit, the second memory cell power supply circuit and the third memory cell power supply circuit are restored to the active state.