Memory circuit and electronic device

• US 10,559,350 B2
• Filed: 09/11/2018
• Issued: 02/11/2020
• Est. Priority Date: 03/14/2018
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Oda, Masato, Yasuda, Shinichi
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US16/127,894
• Publication Number:
  US 20190287610A1
• Time in Patent Office: 518 Days
• Field of Search: 365154, 365155, 365156, 365 51, 365 63
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

Claims

1. A memory circuit comprising:

a first inverter circuit including a first input terminal, a first output terminal, a first p-channel MOS transistor in which a source terminal is connected to a first power supply line and a gate terminal is connected to the first input terminal, and a first n-channel MOS transistor in which a source terminal is connected to a second power supply line, a drain terminal is connected to a drain terminal of the first p-channel MOS transistor, and a gate terminal is connected to the first input terminal;

a second inverter circuit including a second input terminal connected to the first output terminal, a second output terminal connected to the first input terminal, a second p-channel MOS transistor in which a source terminal is connected to the first power supply line and a gate terminal is connected to the second input terminal, and a second n-channel MOS transistor in which a source terminal is connected to the second power supply line, a drain terminal is connected to a drain terminal of the second p-channel MOS transistor, and a gate terminal is connected to the second input terminal;

a third n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the first output terminal and the second input terminal, the source terminal is connected to the drain terminal, and a gate terminal is connected to a first wiring line;

a fourth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the other of the source terminal and the drain terminal of the third re-channel MOS transistor, and the other of the source terminal and the drain terminal is connected to a second wiring line, and a gate terminal is connected to a third wiring line;

a fifth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the second output terminal and the first input terminal, the source terminal is connected to the drain terminal, and a gate terminal is connected to the first wiring line; and

a sixth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the other of the source terminal and the drain terminal of the fifth n-channel MOS transistor, the other of the source terminal and the drain terminal is connected to a fourth wiring line, and a gate terminal is connected to the third wiring line.

2. The memory circuit according to claim 1, further comprising:

a third p-channel MOS transistor, in which a source terminal is connected to a first power supply and a drain terminal is connected to the first wiring line, the third p-channel MOS transistor including a gate insulating film that is thicker than gate insulating films of the first p-channel MOS transistor and the second p-channel MOS transistor; and

a seventh n-channel MOS transistor, in which a source terminal is connected to a second power supply and a drain terminal is connected to the first wiring line, the seventh re-channel MOS transistor including a gate insulating film that is thicker than gate insulating films of the first to fourth n-channel MOS transistors.

3. The memory circuit according to claim 2, further comprising a fourth p-channel MOS transistor in which a gate insulating film is thicker than the gate insulating films of the first p-channel MOS transistor and the second p-channel MOS transistor, the fourth p-channel MOS transistor being disposed between the drain terminal of the third p-channel MOS transistor and the first power supply.

4. The memory circuit according to claim 1, further comprising a control circuit configured to supply a voltage to the third wiring line for turning on the fourth n-channel MOS transistor and the sixth n-channel MOS transistor, supply a first voltage to one of the second wiring line and the fourth wiring line and a second voltage that is lower than the first voltage to the other of the second wiring line and the fourth wiring line, and supply a write voltage to the first wiring line.

5. An electronic device comprising:

the memory circuit according to claim 1;

a memory that stores a program; and

a processor that executes processing on the memory circuit in accordance with the program stored in the memory.