Reduction of multi-threshold voltage patterning damage in nanosheet device structure

• US 10,559,566 B1
• Filed: 09/17/2018
• Issued: 02/11/2020
• Est. Priority Date: 09/17/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, ChoongHyun, Cheng, Kangguo, Li, Juntao, Mochizuki, Shogo
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US16/133,030
• Time in Patent Office: 512 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Devices and methods are provided to fabricate nanosheet field-effect transistor devices having dummy nanosheet channel layers disposed above active nanosheet channel layers to protect the active nanosheet channel layers from oxidation during work function metal patterning processes that are implemented as part of a multi-threshold voltage process module. The dummy nanosheet channel layers have a reduced thickness so that the dummy nanosheet layers do not function as active channel layers of the nanosheet field-effect transistor devices. The dummy nanosheet channel layers serve as an oxygen infusion blocking layers to protect the active nanosheet channel layers from being infused with oxygen and oxidized by a directional plasma etch process performed during a work function metal patterning process.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a nanosheet field-effect transistor device on a semiconductor substrate, wherein the nanosheet field-effect transistor device comprises;

(i) a nanosheet stack structure comprising an active nanosheet channel layer and a dummy nanosheet channel layer disposed above the active nanosheet channel layer;

(ii) a gate structure formed over the nanosheet stack structure, wherein the gate structure comprises a gate sidewall spacer which defines a gate region, conformal gate dielectric layers formed on surfaces of the active nanosheet channel layer and the dummy nanosheet channel layer within the gate region, and a first layer of work function metal formed on the conformal gate dielectric layers and filling the gate region including spaces above and below the active nanosheet channel layers and the dummy nanosheet channel layer with the work function metal;

performing a work function metal patterning process to remove the first layer of work function metal from the gate region, wherein the dummy nanosheet channel layer serves as an oxygen infusion blocking layer to protect the active nanosheet channel layer from being infused with oxygen and oxidized by a directional plasma etch process performed during the work function metal patterning process; and

filling the gate region with a second layer of work function metal which is different from the first layer of work function metal.

2. The method of claim 1, wherein the dummy nanosheet channel layer and the active nanosheet channel layer are formed of epitaxial silicon material, wherein the dummy nanosheet channel layer has a thickness which is less than a thickness of the active nanosheet channel layer, wherein the thickness of the dummy nanosheet channel layer is configured so that the dummy nanosheet channel layer does not function as an active channel layer of the nanosheet field-effect transistor device.

3. The method of claim 2, wherein the dummy nanosheet channel layer has a thickness of about 2 nm to about 4 nm.

4. The method of claim 1, wherein the dummy nanosheet channel layer is one of partial oxidized and completely oxidized as a result of the work function metal patterning process.

5. The method of claim 1, wherein the conformal gate dielectric layers formed on surfaces of the active nanosheet channel layer and the dummy nanosheet channel layer comprise a high-k dielectric material having a dielectric constant greater than about 3.9.

6. The method of claim 5, wherein the conformal gate dielectric layers further comprise an interfacial silicon oxide layer disposed between the high-k gate dielectric material and silicon material of the active nanosheet channel layer and the dummy nanosheet channel layer.

7. The method of claim 1, wherein the first layer of work function metal comprises titanium nitride, and wherein the second layer of work function metal comprises titanium aluminum carbide.

8. The method of claim 1, wherein performing the work function metal patterning process comprises:

performing a first directional plasma etch process to etch an opening in a layer of mask material to form an etch mask, wherein the opening is aligned to the gate region of the nanosheet field-effect transistor device;

performing a wet etch process to etch away the first layer of work function metal from the gate region using an etching solution applied to the gate region through the opening of the etch mask; and

performing a second directional plasma etch process to remove the etch mask;

wherein at least a portion of the dummy nanosheet channel layer comprises an oxide layer formed by oxidation of the dummy nanosheet channel layer as a result of the first and second directional plasma etch processes.

9. A method for fabricating a semiconductor device, comprising:

forming a nanosheet stack structure on a semiconductor substrate, wherein the nanosheet stack structure comprises a stack of alternating semiconductor layers which comprises sacrificial nanosheet layers, active nanosheet channel layers, and a dummy nanosheet channel layer, wherein each active nanosheet channel layer is disposed between sacrificial nanosheet layers in the nanosheet stack structure, and wherein the dummy nanosheet channel layer is formed on an upper sacrificial nanosheet layer of the nanosheet stack structure;

forming a dummy gate over the nanosheet stack structure to define a gate region;

forming a gate sidewall spacer surrounding the dummy gate;

removing the dummy gate to open the gate region and expose a portion of the nanosheet stack structure surrounded by the gate sidewall spacer;

removing the sacrificial nanosheet layers exposed in the gate region to release the active nanosheet channel layers and form spaces above and below the active nanosheet channel layers;

forming conformal gate dielectric layers on exposed surfaces of the dummy nanosheet channel layer and the active nanosheet channel layers within the gate region;

filling the gate region with a first layer of work function metal, wherein the first layer of work function metal fills the spaces above and below the active nanosheet channel layers;

performing a work function metal patterning process to remove the first layer of work function metal from the gate region, wherein the dummy nanosheet channel layer serves as an oxygen infusion blocking layer to protect the active nanosheet channel layers from being infused with oxygen and oxidized by a directional plasma etch process performed during the work function metal patterning process; and

filling the gate region with a second layer of work function metal which is different from the first layer of work function metal.

10. The method of claim 9, wherein the dummy nanosheet channel layer and the active nanosheet channel layers are formed of epitaxial silicon material, wherein the dummy nanosheet channel layer has a thickness which is less than a thickness of the active nanosheet channel layers, wherein the thickness of the dummy nanosheet channel layer is configured so that the dummy nanosheet channel layer does not function as an active channel layer of the nanosheet field-effect transistor device.

11. The method of claim 9, wherein the dummy nanosheet channel layer is one of partial oxidized and completely oxidized as a result of the work function metal patterning process.

12. The method of claim 9, wherein the conformal gate dielectric layers comprise a high-k dielectric material having a dielectric constant greater than about 3.9.

13. The method of claim 12, wherein forming the conformal gate dielectric layers on exposed surfaces of the dummy nanosheet channel layer and the active nanosheet channel layers within the gate region comprises:

performing a chemical oxidation process to oxidize silicon surfaces of the active nanosheet channel layers and the dummy nanosheet channel layer within the gate region and form interfacial oxide layers on the active nanosheet channel layers and the dummy nanosheet channel layer within the gate region; and

conformally depositing a layer of high-k dielectric material to form high-k gate dielectric layers on the interfacial oxide layers of the active nanosheet channel layers and the dummy nanosheet channel layer.

14. The method of claim 9, further comprising performing a silicon thinning process to decrease a thickness of the dummy nanosheet channel layer and the active nanosheet channel layers within the gate region, prior to forming the conformal gate dielectric layers on the surfaces of the dummy nanosheet channel layer and the active nanosheet channel layers within the gate region.

15. The method of claim 9, wherein the first layer of work function metal comprises titanium nitride, and wherein the second layer of work function metal comprises titanium aluminum carbide.

16. The method of claim 9, wherein performing the work function metal patterning process comprises:

performing a first directional plasma etch process to etch an opening in a layer of mask material to form an etch mask, wherein the opening is aligned to the gate region of the nanosheet field-effect transistor device;

performing a wet etch process to etch away the first layer of work function metal from the gate region using an etching solution applied to the gate region through the opening of the etch mask; and

performing a second directional plasma etch process to remove the etch mask;

wherein at least a portion of the dummy nanosheet channel layer comprises an oxide layer formed by oxidation of the dummy nanosheet channel layer as a result of the first and second directional plasma etch processes.