Three-dimensional vertical one-time-programmable memory comprising Schottky diodes
First Claim
Patent Images
1. A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
- a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;
a plurality of vertical address lines in said memory holes and in contact with said antifuse layer;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.
0 Assignments
0 Petitions
Accused Products
Abstract
The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.
40 Citations
13 Claims
-
1. A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
-
a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit; a plurality of memory holes through said horizontal address lines; an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming; a plurality of vertical address lines in said memory holes and in contact with said antifuse layer; a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state; wherein said horizontal and vertical address lines are separated by said antifuse layer only. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
-
a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a metallic material; a plurality of memory holes through said horizontal address lines; an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming; a plurality of vertical address lines in said memory holes and in contact with said antifuse layer, said vertical address lines comprising at least a doped semiconductor material; a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state; wherein said horizontal and vertical address lines are separated by said antifuse layer only. - View Dependent Claims (9, 10)
-
-
11. A three-dimensional vertical one-time-programmable memory (3D-OTPV), comprising:
-
a semiconductor substrate comprising a substrate circuit; a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a doped semiconductor material; a plurality of memory holes through said horizontal address lines; an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming; a plurality of vertical address lines in said memory holes and in contact with said antifuse layer, said vertical address lines comprising at least a metallic material; a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state; wherein said horizontal and vertical address lines are separated by said antifuse layer only. - View Dependent Claims (12, 13)
-
Specification