Semiconductor device with surface insulating film

• US 10,559,668 B2
• Filed: 02/21/2019
• Issued: 02/11/2020
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US16/281,954
• Publication Number:
  US 20190181235A1
• Time in Patent Office: 355 Days
• Field of Search: 257 77, 257328, 257330-334
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 : with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4958 : with a multiple layer structure
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a cell portion arranged at a center portion of the semiconductor substrate in a plan view;

an outer peripheral portion surrounding the cell portion in a plan view;

a plurality of gate trenches formed at the surface of the semiconductor substrate at the cell portion;

a plurality of gate electrodes formed so as to be buried in the plurality of gate trenches;

a surface insulating film with a first thickness formed so as to cover the plurality of gate electrodes at the cell portion, and with a second thickness formed so as to cover the semiconductor substrate at the outer peripheral portion;

a first source portion formed on/over the semiconductor substrate at the cell portion;

a gate portion formed on/over the semiconductor substrate at the outer peripheral portion;

a second source portion formed on/over the semiconductor substrate so as to surround the gate portion at the outer peripheral portion; and

a slit region formed in a uniform width along the gate portion in a plan view, wherein

the first thickness is thinner than the second thickness,

the gate portion has a gate pad that is formed at a center of a first line of the semiconductor substrate, and a gate finger that is formed along with the outer peripheral portion in a plan view,

the plurality of gate trenches are formed on/over the semiconductor substrate at the cell portion in a striped shape, and extends to reach the outer peripheral portion, and

the plurality of gate trenches are formed in a manner running across the gate finger in a region under the gate finger.

2. The semiconductor device according to claim 1, wherein the gate finger has a portion that is formed so as to axisymmetric with respect to the center of the first line in a plan view.

3. The semiconductor device according to claim 2, wherein the first source portion is inclined in a cross sectional view.

4. The semiconductor device according to claim 1, wherein the gate finger is inclined in a cross sectional view.

5. The semiconductor device according to claim 1, wherein a plurality of irregularities are formed on/over a surface of the first source portion in a cross sectional view.

6. The semiconductor device according to claim 5, wherein a surface of the second source portion is less irregular than the surface of the first source portion in a cross sectional view.

7. The semiconductor device according to claim 1, wherein a depth of the gate trench is from 0.7 μ

m to 3 μ

m in a cross sectional view.

8. The semiconductor device according to claim 1, wherein a thickness of the first source portion is from 4 μ

m to 5 μ

m in a cross sectional view.

9. The semiconductor device according to claim 1, further comprising a gate insulating film formed between the gate trench and the gate electrode.

10. The semiconductor device according to claim 9, wherein a width of a bottom of the gate insulating film is wider than a width of a side of the gate insulating film in a cross sectional view.

11. The semiconductor device according to claim 10, wherein the gate insulating film is made of SiO₂.

12. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of SiC, GaN, or diamond.

13. The semiconductor device according to claim 1, further comprising a guard ring that has different conductivity type from the semiconductor substrate, formed at the surface of the semiconductor substrate.

14. The semiconductor device according to claim 1, wherein

the plurality of gate electrodes are made of polysilicon, and

the gate finger includes an aluminum.

15. The semiconductor device according to claim 1, wherein

the first source portion includes an aluminum, and

the second source portion includes an aluminum.

16. The semiconductor device according to claim 1, wherein the first source portion has a quadrangle shape.

17. The semiconductor device according to claim 1, further comprising an overlapping portion that covers the gate electrode of the plurality of gate trenches formed in a region under the gate finger.

18. A semiconductor device, comprising:

a semiconductor substrate made of a wide-bandgap semiconductor;

a cell portion arranged at a center portion of the semiconductor substrate in a plan view;

an outer peripheral portion surrounding the cell portion in a plan view;

a plurality of gate trenches formed at the surface of the semiconductor substrate at the cell portion;

a plurality of gate electrodes formed so as to be buried in the plurality of gate trenches; and

a surface insulating film with a first thickness formed so as to cover the plurality of gate electrodes at the cell portion, and with a second thickness formed so as to cover the semiconductor substrate at the outer peripheral portion;

a first source portion formed on/over the semiconductor substrate at the cell portion;

a gate portion formed on/over the semiconductor substrate at the outer peripheral portion;

a second source portion formed on/over the semiconductor substrate so as to surround the gate portion at the outer peripheral portion; and

a slit region formed in a uniform width along the gate portion in a plan view, wherein

the first thickness is thinner than the second thickness.