Semiconductor device and manufacturing method thereof

• US 10,559,695 B2
• Filed: 05/02/2017
• Issued: 02/11/2020
• Est. Priority Date: 07/31/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyairi, Hidekazu, Miyanaga, Akiharu, Akimoto, Kengo, Shiraishi, Kojiro
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): King, Sun Mi Kim
• Application Number:
  US15/584,264
• Publication Number:
  US 20170236943A1
• Time in Patent Office: 1,015 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer having a first carrier concentration;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer having a second carrier concentration;

a third oxide semiconductor layer over the first oxide semiconductor layer, the third oxide semiconductor layer having a third carrier concentration;

a fourth oxide semiconductor layer over the second oxide semiconductor layer, the fourth oxide semiconductor layer having a fourth carrier concentration;

a fifth oxide semiconductor layer over the third oxide semiconductor layer, the fifth oxide semiconductor layer having a fifth carrier concentration;

an insulating layer over and in contact with the first oxide semiconductor layer;

a source electrode over and in contact with the fourth oxide semiconductor layer; and

a drain electrode over and in contact with the fifth oxide semiconductor layer,

wherein an inner edge of the second oxide semiconductor layer and an inner edge of the third oxide semiconductor layer are over the insulating layer,

wherein an inner edge of the source electrode is deviated from an inner edge of the fourth oxide semiconductor layer and the inner edge of the second oxide semiconductor layer,

wherein an inner edge of the drain electrode is deviated from an inner edge of the fifth oxide semiconductor layer and the inner edge of the third oxide semiconductor layer,

wherein each of the first to fifth oxide semiconductor layers contains indium, gallium, and zinc,

wherein the second carrier concentration is higher than the first carrier concentration and lower than the fourth carrier concentration, and

wherein the third carrier concentration is higher than the first carrier concentration and lower than the fifth carrier concentration.

2. The semiconductor device according to claim 1,

wherein the first carrier concentration is less than 1×

10¹⁷ atoms/cm³, and

wherein the fourth carrier concentration is 1×

10¹⁸ atoms/cm³ or more.

3. The semiconductor device according to claim 1, wherein the gate electrode contains copper.

4. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode has a three-layer structure.

5. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode contains aluminum.

6. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer is in direct contact with the gate insulating layer.

7. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer having a first carrier concentration;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer having a second carrier concentration;

a third oxide semiconductor layer over the first oxide semiconductor layer, the third oxide semiconductor layer having a third carrier concentration;

a fourth oxide semiconductor layer over the second oxide semiconductor layer, the fourth oxide semiconductor layer having a fourth carrier concentration;

a fifth oxide semiconductor layer over the third oxide semiconductor layer, the fifth oxide semiconductor layer having a fifth carrier concentration;

a channel protective layer over and in contact with the first oxide semiconductor layer;

a source electrode electrically connected to the first oxide semiconductor layer through the fourth oxide semiconductor layer and the second oxide semiconductor layer; and

a drain electrode electrically connected to the first oxide semiconductor layer through the fifth oxide semiconductor layer and the third oxide semiconductor layer,

wherein the first oxide semiconductor layer has a first region over which the channel protective layer is present and a second region over which the channel protective layer is absent,

wherein a first thickness of the first region is larger than a second thickness of the second region,

wherein an inner edge of the second oxide semiconductor layer and an inner edge of the third oxide semiconductor layer are over the channel protective layer,

wherein an inner edge of the source electrode is deviated from an inner edge of the fourth oxide semiconductor layer and the inner edge of the second oxide semiconductor layer,

wherein an inner edge of the drain electrode is deviated from an inner edge of the fifth oxide semiconductor layer and the inner edge of the third oxide semiconductor layer,

wherein the second carrier concentration is higher than the first carrier concentration and lower than the fourth carrier concentration,

wherein the third carrier concentration is higher than the first carrier concentration and lower than the fifth carrier concentration, and

wherein each of the first to fifth oxide semiconductor layers contains indium, gallium, and zinc.

8. The semiconductor device according to claim 7,

wherein the first carrier concentration is less than 1×

10¹⁷ atoms/cm³, and

wherein each of the fourth carrier concentration and the fifth carrier concentration is 1×

10¹⁸ atoms/cm³ or more.

9. The semiconductor device according to claim 7, wherein the gate electrode contains copper.

10. The semiconductor device according to claim 7, wherein each of the source electrode and the drain electrode has a three-layer structure.

11. The semiconductor device according to claim 7, wherein each of the source electrode and the drain electrode contains aluminum.

12. The semiconductor device according to claim 7, wherein the second oxide semiconductor layer and the third oxide semiconductor layer are in direct contact with the gate insulating layer.

13. The semiconductor device according to claim 7,

wherein the gate insulating layer comprises a first halogen element,

wherein the channel protective layer comprises a second halogen element,

wherein a peak of a concentration of the first halogen element measured by a secondary ion mass spectrometer is in a range of from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>, and

wherein a peak of a concentration of the second halogen element measured by the secondary ion mass spectrometer is in a range of from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.