Semiconductor device and method for fabricating the same

• US 10,559,752 B2
• Filed: 08/16/2017
• Issued: 02/11/2020
• Est. Priority Date: 12/05/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Il Mok, Park, Tae Jin
• Primary Examiner(s): Muse, Ismail A
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/678,583
• Publication Number:
  US 20180159032A1
• Time in Patent Office: 909 Days
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8616 Thermal insulation means
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides

Abstract

A semiconductor device includes a first word line and a first bit line. The semiconductor device further includes a mold film disposed between the first word line and the first bit line, and a first memory cell disposed in the mold film. The first memory cell includes a first lower electrode in contact with the first word line. Side surfaces of the first lower electrode are in direct contact with the mold film. The first memory cell includes a first phase-change memory in contact with the first lower electrode, a first intermediate electrode in contact with the first phase-change memory, a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, and a first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line.

Claims

1. A semiconductor device, comprising:

a first word line extending in a first direction;

a first bit line extending in a second direction that intersects the first direction, wherein the first bit line and the first word line are spaced apart from each other in a third direction that intersects the first and second directions;

a mold film disposed between the first word line and the first bit line;

a first memory cell disposed in the mold film and including a core hole, wherein the first memory cell comprises;

a first lower electrode in contact with the first word line, wherein side surfaces of the first lower electrode are in direct contact with the mold film,

a first phase-charge memory in contact with the first lower electrode,

a first intermediate electrode in contact with the first phase-change memory,

a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, and

a first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line,

wherein the core hole extends in the first direction through the first lower electrode, the first phase-change memory, the first intermediate electrode, the first OTS and the first upper electrode;

a second bit line extending in the second direction, wherein the second bit line and the first bit line are spaced apart from each other in the first direction; and

a second memory cell disposed between the second bit line and the first word line,

wherein the second memory cell comprises;

a second lower electrode disposed on the first word line, wherein side surfaces of the second lower electrode are in direct contact with the mold film,

a second phase-change memory disposed on the second lower electrode,

a second intermediate electrode disposed on the second phase-change memory,

a second OTS disposed on the second intermediate electrode, and

a second upper electrode disposed between the second OTS and the second bit line, the second upper electrode being in contact with the second OTS and the second bit line.

2. The semiconductor device of claim 1, wherein the third direction is a vertical direction.

3. The semiconductor device of claim 1, wherein the mold film comprises at least one of silicon nitride (SiN), silicon dioxide (SiO2) and silicon (Si).

4. The semiconductor device of claim 1, wherein the first OTS comprises chalcogenide.

5. The semiconductor device of claim 1, wherein a width of the first phase-change memory is greater than a width of the first lower electrode, wherein the width of the first phase-change memory and the width of the first lower electrode extend in the first direction.

6. The semiconductor device of claim 1, wherein a height of the first lower electrode is a same as a height of the second lower electrode, wherein the height of the first lower electrode and the height of the second lower electrode extend in the third direction.

7. The semiconductor device of claim 1, further comprising a second bit line extending in the second direction, wherein the second bit line and the first bit line are spaced apart from each other in the first direction,

wherein an upper surface of the first memory cell is in contact with both the first and second bit lines.

8. The semiconductor device of claim 7, wherein an inner mold film is disposed in the core hole.

9. The semiconductor device of claim 8, wherein a bottom surface of the core hole is formed by the first lower electrode.

10. A semiconductor device, comprising:

a first word line extending in a first direction;

a second word line extending in the first direction and disposed on the first word line, wherein the second word line is parallel to the first word line;

a first bit line extending in a second direction, which intersects the first direction, and disposed between the first and second word lines;

a first memory cell disposed between the first word line and the first bit line, wherein the first memory cell comprises;

a first lower electrode disposed on the first word line, wherein the first lower electrode includes a first width extending in the first direction,

a first phase-change memory disposed on the first lower electrode, wherein the first phase-change memory includes a second width that is greater than the first width,

a first OTS disposed on the first phase-change memory, and

a first upper electrode disposed between the first OTS and the first bit line; and

a second memory cell disposed between the second word line and the first bit line, wherein the second memory cell comprises;

a second lower electrode disposed on the first bit line, wherein the second lower electrode includes a third width extending in the second direction,

a second phase-change memory disposed on the second lower electrode, wherein the second phase-change memory includes a fourth width that is greater than the third width,

a second OTS disposed on the second phase-change memory, and

a second upper electrode disposed between the second OTS and the second word line.

11. The semiconductor device of claim 10, wherein the first memory cell overlaps the second memory cell.

12. The semiconductor device of claim 10, wherein the first lower electrode has a U-shape, from a cross sectional view along the first direction.

13. The semiconductor device of claim 12, wherein the second lower electrode has a U-shape, from a cross sectional view along the second direction.

14. A semiconductor device, comprising:

a first word line extending in a first direction;

a first bit line extending in a second direction crossing the first direction, wherein the first bit line is disposed above the first word line;

a first memory cell disposed on the first word line and comprising;

a core hole, wherein an inner mold film is disposed in the core hole,

a first lower electrode disposed on the first word line and having a first height from an upper surface of the first word line, wherein the first lower electrode is in contact with the inner mold film,

a first phase-change memory disposed on the first lower electrode at the first height,

a first intermediate electrode disposed on the first phase-change memory,

a first ovonic threshold switch (OTS) disposed on the first intermediate electrode, and

a first upper electrode disposed on the first OTS; and

an outer mold film surrounding the first memory cell.

15. The semiconductor device of claim 14, further comprising a second word line disposed on the first word line and extending in the first direction;

and

a second memory cell surrounded by the mold film, disposed between the second word line and the first bit line, and comprising;

a second lower electrode disposed on the first bit line and having a second height from the first bit line,

a second phase-change memory disposed on the second lower electrode at the second height,

a second intermediate electrode disposed on the second phase-change memory,

a second ovonic threshold switch (OTS) disposed on the second intermediate electrode, and

a second upper electrode disposed between the second OTS and the second word line.

16. The semiconductor device of claim 15 wherein the first height and the second height are substantially the same.

17. The semiconductor device of claim 15, wherein the first memory cell is divided into a first-first memory cell and a first-second memory cell by a first cell separator.

18. The semiconductor device of claim 17, wherein the second memory cell overlaps the first memory cell, and

the second memory cell is divided into a second-first memory cell and a second-second memory cell by a second cell separator.