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Semiconductor device and method for fabricating the same

  • US 10,559,752 B2
  • Filed: 08/16/2017
  • Issued: 02/11/2020
  • Est. Priority Date: 12/05/2016
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a first word line extending in a first direction;

    a first bit line extending in a second direction that intersects the first direction, wherein the first bit line and the first word line are spaced apart from each other in a third direction that intersects the first and second directions;

    a mold film disposed between the first word line and the first bit line;

    a first memory cell disposed in the mold film and including a core hole, wherein the first memory cell comprises;

    a first lower electrode in contact with the first word line, wherein side surfaces of the first lower electrode are in direct contact with the mold film,a first phase-charge memory in contact with the first lower electrode,a first intermediate electrode in contact with the first phase-change memory,a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, anda first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line,wherein the core hole extends in the first direction through the first lower electrode, the first phase-change memory, the first intermediate electrode, the first OTS and the first upper electrode;

    a second bit line extending in the second direction, wherein the second bit line and the first bit line are spaced apart from each other in the first direction; and

    a second memory cell disposed between the second bit line and the first word line,wherein the second memory cell comprises;

    a second lower electrode disposed on the first word line, wherein side surfaces of the second lower electrode are in direct contact with the mold film,a second phase-change memory disposed on the second lower electrode,a second intermediate electrode disposed on the second phase-change memory,a second OTS disposed on the second intermediate electrode, anda second upper electrode disposed between the second OTS and the second bit line, the second upper electrode being in contact with the second OTS and the second bit line.

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