Level shift circuit

• US 10,560,084 B2
• Filed: 09/06/2018
• Issued: 02/11/2020
• Est. Priority Date: 09/08/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Yagi, Toshihiro
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/123,266
• Publication Number:
  US 20190081622A1
• Time in Patent Office: 523 Days
• Field of Search: None
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 19/017 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.

Claims

1. A level shift circuit comprising:

a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;

a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;

a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;

a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;

a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;

a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and

a potential adjusting circuit that is electrically connected to at least the second node, and

wherein the potential adjusting circuit is a charging circuit electrically connected to the second node,

the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,

the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.

2. The level shift circuit according to claim 1, wherein

the switch is maintained to be in an on state in a third time period from before a second timing which is after the first timing and at which the output terminal transitions from the first level to the second level to the second timing, and is maintained to be in an off state in a fourth time period following the third time period.

3. The level shift circuit according to claim 1, further comprising

a pulse generator electrically connected to a control node of the switch.

4. The level shift circuit according to claim 3, wherein

the pulse generator comprises

a logic circuit that includes a first input node and a second input node,

a line connected to the first input node, and

a delay line that is connected to the second input node and includes a delay element and a MOS transistor serving as a load capacitance.

5. The level shift circuit according to claim 1, wherein

a voltage corresponding to the second power-supply potential is supplied to the second node via the switch.

6. The level shift circuit according to claim 1, wherein

the potential adjusting circuit is a pull-up circuit electrically connected to the second node and the fifth node.

7. The level shift circuit according to claim 6, wherein

the pull-up circuit comprises

a first pull-up switch electrically inserted between the node to be the second power-supply potential and the second node, and

a second pull-up switch electrically inserted between the node to be the second power-supply potential and the fifth node.

8. The level shift circuit according to claim 7, further comprising

a control circuit configured to turn on the first pull-up switch and the second pull-up switch in accordance with a potential difference between the first power-supply potential and the second power-supply potential.

9. The level shift circuit according to claim 8, wherein

the control circuit is configured to turn on the first pull-up switch and the second pull-up switch in accordance with the potential difference between the first power-supply potential and the second power-supply potential being smaller than a threshold.

10. The level shift circuit according to claim 9, wherein

the control circuit is configured to turn off the first pull-up switch and the second pull-up switch in accordance with the potential difference between the first power-supply potential and the second power-supply potential being larger than the threshold.

11. The level shift circuit according to claim 1, wherein

the second power-supply potential is higher than the first power-supply potential.

12. A level shift circuit comprising:

a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a node to be a second power-supply potential at a source, and electrically connected to a second node at a drain;

a first NMOS transistor electrically connected to the first node at a gate and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;

a second PMOS transistor electrically connected to a third node at a gate, electrically connected to the second node at a source, and electrically connected to the output terminal at a drain;

a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to a fifth node at a drain;

a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;

a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the fifth node at a source, and electrically connected to the third node at a drain; and

a potential adjusting circuit that is electrically connected to the second node and the fifth node.

13. The level shift circuit according to claim 12, wherein

the potential adjusting circuit is a pull-up circuit that pulls up a potential at the second node and pulls up a potential at the fifth node.

14. The level shift circuit according to claim 13, wherein

the pull-up circuit comprises

a first pull-up switch electrically inserted between the node to be the second power-supply potential and the second node, and

a second pull-up switch electrically inserted between the node to be the second power-supply potential and the fifth node.

15. The level shift circuit according to claim 14, further comprising

a control circuit configured to turn on the first pull-up switch and the second pull-up switch in accordance with a potential difference between the first power-supply potential and the second power-supply potential.

16. The level shift circuit according to claim 15, wherein

the control circuit is configured to turn on the first pull-up switch and the second pull-up switch in accordance with the potential difference between the first power-supply potential and the second power-supply potential being smaller than a threshold.

17. The level shift circuit according to claim 16, wherein

the control circuit is configured to turn off the first pull-up switch and the second pull-up switch in accordance with the potential difference between the first power-supply potential and the second power-supply potential being larger than the threshold.