Level shift circuit
First Claim
1. A level shift circuit comprising:
- a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;
a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;
a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;
a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;
a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;
a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and
a potential adjusting circuit that is electrically connected to at least the second node, andwherein the potential adjusting circuit is a charging circuit electrically connected to the second node,the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.
2 Assignments
0 Petitions
Accused Products
Abstract
According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.
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Citations
17 Claims
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1. A level shift circuit comprising:
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a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output; a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain; a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain; a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain; a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain; a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and a potential adjusting circuit that is electrically connected to at least the second node, and wherein the potential adjusting circuit is a charging circuit electrically connected to the second node, the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node, the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A level shift circuit comprising:
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a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a node to be a second power-supply potential at a source, and electrically connected to a second node at a drain; a first NMOS transistor electrically connected to the first node at a gate and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output; a second PMOS transistor electrically connected to a third node at a gate, electrically connected to the second node at a source, and electrically connected to the output terminal at a drain; a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to a fifth node at a drain; a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain; a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the fifth node at a source, and electrically connected to the third node at a drain; and a potential adjusting circuit that is electrically connected to the second node and the fifth node. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification