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Level shift circuit

  • US 10,560,084 B2
  • Filed: 09/06/2018
  • Issued: 02/11/2020
  • Est. Priority Date: 09/08/2017
  • Status: Active Grant
First Claim
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1. A level shift circuit comprising:

  • a first PMOS transistor electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, electrically connected to a second node at a source, and electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential different from the first power-supply potential is output;

    a first NMOS transistor electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain;

    a second PMOS transistor electrically connected to a third node at a gate, electrically connected to a node to be the second power-supply potential at a source, and electrically connected to the second node at a drain;

    a third PMOS transistor electrically connected at a gate to a fourth node to which a second signal having an amplitude to be the first power-supply potential and being logical inversion of the first signal is input, electrically connected to a fifth node at a source, and electrically connected to the third node at a drain;

    a second NMOS transistor electrically connected to the fourth node at a gate and electrically connected to the third node at a drain;

    a fourth PMOS transistor electrically connected to the output terminal at a gate, electrically connected to the node to be the second power-supply potential at a source, and electrically connected to the fifth node at a drain; and

    a potential adjusting circuit that is electrically connected to at least the second node, andwherein the potential adjusting circuit is a charging circuit electrically connected to the second node,the charging circuit includes a switch electrically inserted between the node to be the second power-supply potential and the second node,the switch is maintained to be in an on state in a first time period from before a first timing at which the output terminal transitions from a first level to a second level to the first timing, and is maintained to be in an off state in a second time period following the first time period.

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