Circuits for efficient detection of vector signaling codes for chip-to-chip communication

• US 10,560,293 B2
• Filed: 12/19/2018
• Issued: 02/11/2020
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Ulrich, Roger, Hunt, Peter
• Primary Examiner(s): Wong, Linda
• Application Number:
  US16/225,206
• Publication Number:
  US 20190123943A1
• Time in Patent Office: 419 Days
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 2025/03789 Codes therefore
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Claims

1. A method comprising:

obtaining a set of at least four input signals via respective wires of a multi-wire bus;

generating a set of comparator outputs at a set of multi-input comparators (MICs) in a first mode of operation, each MIC of the set of MICs connected to all of the wires of the multi-wire bus according to a respective input permutation of a plurality of input permutations associated with a vector signaling code, each MIC of the set of MICs generating a respective comparator output by forming a computation of the plurality set of at least four input signals received via the multi-wire bus according to the respective input permutation;

generating at least two differential outputs at the set of MICs in a second mode of operation, each differential output generated by comparing signal values of input signals obtained on a respective pair of wires of the multi-wire bus; and

obtaining a selection signal to configured the set of MICs to operate in the first or second mode of operation, wherein the selection signal disables one of the MICs in the second mode of operation.

2. The method of claim 1, wherein configuring a corresponding MIC of the set of MICs to operate in the second mode of operation comprises disconnecting signals that are not in the respective pair of wires from the corresponding MIC.

3. The method of claim 1, further comprising attenuating the set of input signals in the second mode of operation.

4. The method of claim 1, wherein the set of MICs generate three comparator outputs in the first mode of operation and two differential outputs in the second mode of operation.

5. The method of claim 1, wherein the set of MICs generate the set of comparator outputs on a differential output node via a plurality of differential pairs of transistors, each transistor of the plurality of differential pairs of transistors receiving a respective input signal of the set of at least four input signals.

6. The method of claim 5, wherein each transistor in the plurality of differential pairs of transistors are biased in a linear amplification mode.

7. An apparatus comprising:

a multi-wire bus configured to provide a set of at least four input signals, each input signal of the set of at least four input signals provided via a respective wire of the multi-wire bus; and

a set of multi-input comparators (MICs), each MIC of the set of MICs connected to all of the wires of the multi-wire bus according to a respective input permutation of a plurality of input permutations associated with a vector signaling code, the set of MICs configured to receive a selection signal for configuring the set of MICs to operated in a first or a second mode of operation, the set of MICs configured to;

generate a set of comparator outputs in the first mode of operation, each comparator output generated by a corresponding MIC forming a computation of the set of at least four input signals according to the associated input permutation; and

generate at least two differential outputs in the second mode of operation, each differential output generated by comparing signal values of input signals obtained on a respective pair of wires of the multi-wire bus, the selection signal further configured to disable at least one MIC of the set of MICs in the second mode of operation.

8. The apparatus of claim 7, wherein the selection signal is configured to disconnect signals that are not in the respective pair of wires from the corresponding MIC in the second mode of operation.

9. The apparatus of claim 7, further comprising an attenuation circuit configured to attenuate the set of input signals in the second mode of operation.

10. The apparatus of claim 7, wherein the set of MICs is configured to generate a set of three comparator outputs in the first mode of operation and to generate two differential outputs in the second mode of operation.

11. The apparatus of claim 7, wherein each MIC of the set of MICs comprises a plurality of differential pairs of transistors connected to a differential output node, the plurality of differential pairs of transistors receiving the set of at least four input signals according to the associated input permutation.

12. The apparatus of claim 11, wherein each transistor in the plurality of differential pairs of transistors are biased in a linear amplification mode.