Processor for enhancing network security

• US 10,560,475 B2
• Filed: 10/10/2017
• Issued: 02/11/2020
• Est. Priority Date: 03/07/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zand, Kambiz
• Assistant Examiner(s): Le, Thanh H
• Application Number:
  US15/729,640
• Publication Number:
  US 20180034831A1
• Time in Patent Office: 854 Days
• CPC Class Codes: G06F 21/564 by virus signature recognition
• CPC Class Codes: G06V 10/955 using specific electronic processors
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H04L 63/145 the attack involving the propagation of malware through the network, e.g. viruses, trojans or worms
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Claims

1. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet;

a semiconductor substrate with transistors thereon; and

, at least one thousand storage-processing units (SPU'"'"'s) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU'"'"'s comprising;

at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;

a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;

a plurality of inter-storage-processor (ISP) connections for communicatively coupling said 3D-M array and said pattern-processing circuit;

wherein said pattern-processing circuit is disposed on said semiconductor substrate;

said 3D-M array is stacked above said pattern-processing circuit; and

, said processor comprises no more semiconductor substrate other than said semiconductor substrate.

2. The processor according to claim 1, wherein said pattern-processing circuit includes at least a text-matching circuit or a code-matching circuit.

3. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a comparator, a content-addressable-memory (CAM), or a finite-state automata (FSA) circuit.

4. The processor according to claim 1, wherein said 3D-M array is a three-dimensional horizontal memory (3D-M_H) array.

5. The processor according to claim 1, wherein said 3D-M array is a three-dimensional vertical memory (3D-M_V) array.

6. The processor according to claim 1, wherein said 3D-M array at least partially covers said pattern-processing circuit.

7. The processor according to claim 1, wherein said pattern-processing circuit is covered by at least two 3D-M arrays.

8. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet;

a semiconductor substrate with transistors thereon; and

, a plurality of storage-processing units (SPU'"'"'s) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU'"'"'s comprising;

at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;

a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;

at least one thousand contact vias for communicatively coupling said 3D-M array and said pattern-processing circuit;

wherein said pattern-processing circuit is disposed on said semiconductor substrate;

said 3D-M array is stacked above said pattern-processing circuit; and

, said processor comprises no more semiconductor substrate other than said semiconductor substrate.

9. The processor according to claim 8, wherein said pattern-processing circuit includes at least a text-matching circuit, and/or a code-matching circuit.

10. The processor according to claim 8, wherein said pattern-processing circuit comprises at least a comparator, a content-addressable-memory (CAM), or a finite-state automata (FSA) circuit.

11. The processor according to claim 8, wherein said 3D-M array is a three-dimensional horizontal memory (3D-M_H) array.

12. The processor according to claim 8, wherein said 3D-M array is a three-dimensional vertical memory (3D-M_V) array.

13. The processor according to claim 8, wherein said 3D-M array at least partially covers said pattern-processing circuit.

14. The processor according to claim 8, wherein said pattern-processing circuit is covered by at least two 3D-M arrays.

15. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet;

a semiconductor substrate with transistors thereon; and

, a plurality of storage-processing units (SPU'"'"'s) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU'"'"'s comprising;

at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;

a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;

a plurality of contact vias for communicatively coupling said 3D-M array and said pattern-processing circuit, wherein the length of said contact vias is on the order of a micron;

wherein said pattern-processing circuit is disposed on said semiconductor substrate;

said 3D-M array is stacked above said pattern-processing circuit; and

, said data storage comprises no more semiconductor substrate other than said semiconductor substrate.

16. The processor according to claim 15, wherein said pattern-processing circuit includes at least a text-matching circuit, and/or a code-matching circuit.

17. The processor according to claim 15, wherein said 3D-M array is a three-dimensional horizontal memory (3D-M_H) array.

18. The processor according to claim 15, wherein said 3D-M array is a three-dimensional vertical memory (3D-M_V) array.

19. The processor according to claim 15, wherein said 3D-M array at least partially covers said pattern-processing circuit.

20. The processor according to claim 15, wherein said pattern-processing circuit is covered by at least two 3D-M arrays.