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Processor for enhancing network security

  • US 10,560,475 B2
  • Filed: 10/10/2017
  • Issued: 02/11/2020
  • Est. Priority Date: 03/07/2016
  • Status: Active Grant
First Claim
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1. A processor for enhancing network security, comprising an input bus for transferring at least a portion of at least a network packet;

  • a semiconductor substrate with transistors thereon; and

    , at least one thousand storage-processing units (SPU'"'"'s) disposed on said semiconductor substrate and communicatively coupled with said input bus, each of said SPU'"'"'s comprising;

    at least a three-dimensional memory (3D-M) array for storing at least a portion of a rule pattern;

    a pattern-processing circuit for performing pattern matching or pattern recognition on said network packet against said rule pattern;

    a plurality of inter-storage-processor (ISP) connections for communicatively coupling said 3D-M array and said pattern-processing circuit;

    wherein said pattern-processing circuit is disposed on said semiconductor substrate;

    said 3D-M array is stacked above said pattern-processing circuit; and

    , said processor comprises no more semiconductor substrate other than said semiconductor substrate.

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